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Message-ID: <CAPDyKFoR+0xtmjESCfk5-aUYhsjcc6ATevRoRpw+atCjmz5yrQ@mail.gmail.com>
Date: Fri, 9 Jun 2023 01:10:18 +0200
From: Ulf Hansson <ulf.hansson@...aro.org>
To: Wenbin Mei <wenbin.mei@...iatek.com>
Cc: Chaotian Jing <chaotian.jing@...iatek.com>,
Matthias Brugger <matthias.bgg@...il.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>,
Adrian Hunter <adrian.hunter@...el.com>,
Ritesh Harjani <riteshh@...eaurora.org>,
Asutosh Das <asutoshd@...eaurora.org>,
linux-mmc@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org,
kernel test robot <lkp@...el.com>
Subject: Re: [PATCH v5 1/1] mmc: mtk-sd: reduce CIT for better performance
On Tue, 6 Jun 2023 at 13:32, Wenbin Mei <wenbin.mei@...iatek.com> wrote:
>
> CQHCI_SSC1 indicates to CQE the polling period to use when using periodic
> SEND_QUEUE_STATUS(CMD13) polling.
> Since MSDC CQE uses msdc_hclk as ITCFVAL, so driver should use hclk
> frequency to get the actual time.
> The default value 0x1000 that corresponds to 150us for MediaTek SoCs, let's
> decrease it to 0x40 that corresponds to 2.35us, which can improve the
> performance of some eMMC devices.
>
> Reported-by: kernel test robot <lkp@...el.com>
> Signed-off-by: Wenbin Mei <wenbin.mei@...iatek.com>
Applied for next, thanks!
Kind regards
Uffe
> ---
> the previous patche link:
> v4: https://patchwork.kernel.org/project/linux-mediatek/patch/20230605121442.23622-1-wenbin.mei@mediatek.com/
> v3: https://patchwork.kernel.org/project/linux-mediatek/patch/20230605060107.22044-1-wenbin.mei@mediatek.com/
> v2: https://patchwork.kernel.org/project/linux-mediatek/patch/20230510015851.11830-1-wenbin.mei@mediatek.com/
> v1: https://patchwork.kernel.org/project/linux-mediatek/patch/20230419063048.10516-1-wenbin.mei@mediatek.com/
> ---
> drivers/mmc/host/cqhci.h | 2 ++
> drivers/mmc/host/mtk-sd.c | 47 +++++++++++++++++++++++++++++++++++++++
> 2 files changed, 49 insertions(+)
>
> diff --git a/drivers/mmc/host/cqhci.h b/drivers/mmc/host/cqhci.h
> index ba9387ed90eb..e35c655edefc 100644
> --- a/drivers/mmc/host/cqhci.h
> +++ b/drivers/mmc/host/cqhci.h
> @@ -23,6 +23,8 @@
> /* capabilities */
> #define CQHCI_CAP 0x04
> #define CQHCI_CAP_CS 0x10000000 /* Crypto Support */
> +#define CQHCI_CAP_ITCFMUL GENMASK(15, 12)
> +#define CQHCI_ITCFMUL(x) FIELD_GET(CQHCI_CAP_ITCFMUL, (x))
>
> /* configuration */
> #define CQHCI_CFG 0x08
> diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
> index 8ce864169986..b582f19f82f2 100644
> --- a/drivers/mmc/host/mtk-sd.c
> +++ b/drivers/mmc/host/mtk-sd.c
> @@ -473,6 +473,7 @@ struct msdc_host {
> struct msdc_tune_para def_tune_para; /* default tune setting */
> struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
> struct cqhci_host *cq_host;
> + u32 cq_ssc1_time;
> };
>
> static const struct mtk_mmc_compatible mt2701_compat = {
> @@ -2450,9 +2451,50 @@ static void msdc_hs400_enhanced_strobe(struct mmc_host *mmc,
> }
> }
>
> +static void msdc_cqe_cit_cal(struct msdc_host *host, u64 timer_ns)
> +{
> + struct mmc_host *mmc = mmc_from_priv(host);
> + struct cqhci_host *cq_host = mmc->cqe_private;
> + u8 itcfmul;
> + unsigned long hclk_freq;
> + u64 value;
> +
> + /*
> + * On MediaTek SoCs the MSDC controller's CQE uses msdc_hclk as ITCFVAL
> + * so we multiply/divide the HCLK frequency by ITCFMUL to calculate the
> + * Send Status Command Idle Timer (CIT) value.
> + */
> + hclk_freq = clk_get_rate(host->h_clk);
> + itcfmul = CQHCI_ITCFMUL(cqhci_readl(cq_host, CQHCI_CAP));
> + switch (itcfmul) {
> + case 0x0:
> + do_div(hclk_freq, 1000);
> + break;
> + case 0x1:
> + do_div(hclk_freq, 100);
> + break;
> + case 0x2:
> + do_div(hclk_freq, 10);
> + break;
> + case 0x3:
> + break;
> + case 0x4:
> + hclk_freq = hclk_freq * 10;
> + break;
> + default:
> + host->cq_ssc1_time = 0x40;
> + return;
> + }
> +
> + value = hclk_freq * timer_ns;
> + do_div(value, 1000000000);
> + host->cq_ssc1_time = value;
> +}
> +
> static void msdc_cqe_enable(struct mmc_host *mmc)
> {
> struct msdc_host *host = mmc_priv(mmc);
> + struct cqhci_host *cq_host = mmc->cqe_private;
>
> /* enable cmdq irq */
> writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN);
> @@ -2462,6 +2504,9 @@ static void msdc_cqe_enable(struct mmc_host *mmc)
> msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0);
> /* default read data timeout 1s */
> msdc_set_timeout(host, 1000000000ULL, 0);
> +
> + /* Set the send status command idle timer */
> + cqhci_writel(cq_host, host->cq_ssc1_time, CQHCI_SSC1);
> }
>
> static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery)
> @@ -2803,6 +2848,8 @@ static int msdc_drv_probe(struct platform_device *pdev)
> /* cqhci 16bit length */
> /* 0 size, means 65536 so we don't have to -1 here */
> mmc->max_seg_size = 64 * 1024;
> + /* Reduce CIT to 0x40 that corresponds to 2.35us */
> + msdc_cqe_cit_cal(host, 2350);
> }
>
> ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
> --
> 2.25.1
>
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