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Message-ID: <b61c7d8c-85e7-2248-d386-ffec8c275aa4@collabora.com>
Date: Thu, 8 Jun 2023 14:13:56 +0200
From: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>
To: Chen-Yu Tsai <wenst@...omium.org>,
Matthias Brugger <matthias.bgg@...il.com>
Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>
Subject: Re: [PATCH 4/4] arm64: dts: mediatek: mt8186: Wire up GPU
voltage/frequency scaling
Il 07/06/23 11:06, Chen-Yu Tsai ha scritto:
> Add the GPU's OPP table. This is from the downstream ChromeOS kernel,
> adapted to the new upstream opp-supported-hw binning format. Also add
> dynamic-power-coefficient for the GPU.
>
> Also add label for mfg1 power domain. This is to be used at the board
> level to add a regulator supply for the power domain.
>
> Signed-off-by: Chen-Yu Tsai <wenst@...omium.org>
> ---
> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 140 ++++++++++++++++++++++-
> 1 file changed, 139 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> index c58d7eb87b1d..a34489e27cd4 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> @@ -695,6 +695,142 @@ clk32k: oscillator-32k {
> clock-output-names = "clk32k";
> };
>
> + gpu_opp_table: opp-table-gpu {
> + compatible = "operating-points-v2";
> +
> + opp-299000000 {
> + opp-hz = /bits/ 64 <299000000>;
> + opp-microvolt = <612500>;
> + opp-supported-hw = <0x38>;
For all of the OPPs that are supposed to be supported by all speed-bins, you don't
need to restrict them to all "known" bins.
Please change opp-supported-hw from <0x38> to <0xff>, which literally means
just "applies to all revisions".
> + };
..snip...
> +
> + opp-900000000-3 {
What about calling those like "opp-900000000-bin3"?
Makes it clear that it's tied to what MediaTek calls a speedbin "3" (as we're
interpreting the values in the nvmem driver to make them compatible with the
opp-supported-hw's expectations).
Cheers,
Angelo
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