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Message-ID: <20230612204252.kb57m72ehazt4bco@halaney-x13s>
Date: Mon, 12 Jun 2023 15:42:52 -0500
From: Andrew Halaney <ahalaney@...hat.com>
To: Bartosz Golaszewski <brgl@...ev.pl>
Cc: Vinod Koul <vkoul@...nel.org>,
Bhupesh Sharma <bhupesh.sharma@...aro.org>,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
"David S . Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Kishon Vijay Abraham I <kishon@...nel.org>,
Giuseppe Cavallaro <peppe.cavallaro@...com>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
Jose Abreu <joabreu@...opsys.com>, netdev@...r.kernel.org,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-phy@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org,
linux-stm32@...md-mailman.stormreply.com,
Bartosz Golaszewski <bartosz.golaszewski@...aro.org>
Subject: Re: [PATCH 14/26] net: stmmac: dwmac-qcom-ethqos: add optional
phyaux clock
On Mon, Jun 12, 2023 at 11:23:43AM +0200, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <bartosz.golaszewski@...aro.org>
>
> On sa8775p we don't use the RGMII clock but have an additional PHYAUX
> clock so add support for it to the driver.
>
> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@...aro.org>
> ---
> .../ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
> index 252dca400071..2f6b9b419601 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
> @@ -94,6 +94,7 @@ struct qcom_ethqos {
>
> unsigned int rgmii_clk_rate;
> struct clk *rgmii_clk;
> + struct clk *phyaux_clk;
> struct phy *serdes_phy;
> unsigned int speed;
>
> @@ -604,6 +605,13 @@ static int ethqos_clks_config(void *priv, bool enabled)
> return ret;
> }
>
> + ret = clk_prepare_enable(ethqos->phyaux_clk);
> + if (ret) {
> + clk_disable_unprepare(ethqos->rgmii_clk);
> + dev_err(ðqos->pdev->dev, "phyaux enable failed\n");
> + return ret;
> + }
> +
> /* Enable functional clock to prevent DMA reset to timeout due
> * to lacking PHY clock after the hardware block has been power
> * cycled. The actual configuration will be adjusted once
> @@ -611,6 +619,7 @@ static int ethqos_clks_config(void *priv, bool enabled)
> */
> ethqos_set_func_clk_en(ethqos);
> } else {
> + clk_disable_unprepare(ethqos->phyaux_clk);
> clk_disable_unprepare(ethqos->rgmii_clk);
> }
>
> @@ -669,6 +678,12 @@ static int qcom_ethqos_probe(struct platform_device *pdev)
> goto out_config_dt;
> }
>
> + ethqos->phyaux_clk = devm_clk_get_optional(dev, "phyaux");
> + if (IS_ERR(ethqos->phyaux_clk)) {
> + ret = PTR_ERR(ethqos->phyaux_clk);
> + goto out_config_dt;
> + }
> +
Similar comment to the prior patch about whether or not this should be
optional (or selected via platform compatible and required),
otherwise looks good.
> ret = ethqos_clks_config(ethqos, true);
> if (ret)
> goto out_config_dt;
> --
> 2.39.2
>
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