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Message-ID: <CAK9=C2WR+1ZGp+db7axszzthT=G8M0134+frxBNq1YS0FnF7jg@mail.gmail.com>
Date: Tue, 13 Jun 2023 13:48:32 +0530
From: Anup Patel <apatel@...tanamicro.com>
To: Conor Dooley <conor.dooley@...rochip.com>
Cc: Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Thomas Gleixner <tglx@...utronix.de>,
Marc Zyngier <maz@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Robin Murphy <robin.murphy@....com>,
Joerg Roedel <joro@...tes.org>, Will Deacon <will@...nel.org>,
Frank Rowand <frowand.list@...il.com>,
Atish Patra <atishp@...shpatra.org>,
Andrew Jones <ajones@...tanamicro.com>,
Anup Patel <anup@...infault.org>,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, iommu@...ts.linux.dev
Subject: Re: [PATCH v3 04/11] dt-bindings: interrupt-controller: Add RISC-V
incoming MSI controller
On Wed, May 10, 2023 at 5:46 PM Conor Dooley <conor.dooley@...rochip.com> wrote:
>
> Hey Anup,
>
> On Mon, May 08, 2023 at 07:58:35PM +0530, Anup Patel wrote:
> > + interrupts-extended:
> > + minItems: 1
> > + maxItems: 16384
> > + description:
> > + This property represents the set of CPUs (or HARTs) for which given
> > + device tree node describes the IMSIC interrupt files. Each node pointed
> > + to should be a riscv,cpu-intc node, which has a riscv node (i.e. RISC-V
> > + HART) as parent.
>
> One minor nit here about wording - "riscv node" doesn't seem
> particularly clear to me, should it be s/riscv node/cpu node/?
Okay, I will update.
>
> My only thing last time around was my misunderstanding, and you also
> appear to have resolved Rob's complaints, so:
> Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>
>
> Just to note, it'd be great if you could CC me on series that I've
> already reviewed when you resubmit them?
> Although in this case, if you ran get_maintainer.pl on v6.4-rc1 it'd have
> told you to CC me anyway ;)
>
> Thanks,
> Conor.
Regards,
Anup
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