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Message-ID: <ZIsiEIhmpS7DSs6R@lizhi-Precision-Tower-5810>
Date:   Thu, 15 Jun 2023 10:37:04 -0400
From:   Frank Li <Frank.li@....com>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Cc:     vkoul@...nel.org, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, dmaengine@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        peng.fan@....com, joy.zou@....com, shenwei.wang@....com,
        imx@...ts.linux.dev
Subject: Re: [PATCH v6 12/12] dt-bindings: fsl-dma: fsl-edma: add edma3
 compatible string

On Thu, Jun 15, 2023 at 12:52:18PM +0200, Krzysztof Kozlowski wrote:
> On 14/06/2023 21:35, Frank Li wrote:
> > +        # It is not necessary to write the interrupt name for each channel.
> > +        # instead, you can simply maintain the sequential IRQ numbers as
> > +        # defined for the DMA channels.
> > +        interrupt-names: false
> > +        clock-names:
> 
> items:
>   - const: dma
> 
> clocks:
>   maxItems: 1
> 
> You do not allow more than one clock, right?

Yes, at least now. Only 1 clock needed.

> 
> > +          const: dma
> > +    else:
> 
> You already have two ifs, so you should not have else here, but rather
> make each if clause proper for your setup.
> 
> BTW, the amount of differences point to very complicated schema, so you
> should think whether it makes sense to keep binding growing in the first
> place.

Any good ways if don't growing binding at the first place?

> 
> > +      properties:
> > +        reg:
> > +          minItems: 2
> > +          maxItems: 3
> > +        interrupts:
> > +          minItems: 2
> > +          maxItems: 17
> 
> missing clocks restriction to minItems: 2
> 
> 
> > +        "#dma-cells":
> > +          const: 2
> > +        dma-channels:
> > +          const: 32
> > +
> 
> 
> 
> Best regards,
> Krzysztof
> 

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