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Message-ID: <CAP-5=fUZ+erp_cNoy4sSqPpZN8BmiPLui42o8+GtPzYj0gXmfw@mail.gmail.com>
Date: Wed, 14 Jun 2023 23:03:22 -0700
From: Ian Rogers <irogers@...gle.com>
To: Ravi Bangoria <ravi.bangoria@....com>
Cc: acme@...nel.org, jolsa@...nel.org, namhyung@...nel.org,
peterz@...radead.org, james.clark@....com, alisaidi@...zon.com,
leo.yan@...aro.org, adrian.hunter@...el.com,
kan.liang@...ux.intel.com, mark.rutland@....com,
maddy@...ux.ibm.com, tmricht@...ux.ibm.com,
linux-perf-users@...r.kernel.org, linux-kernel@...r.kernel.org,
sandipan.das@....com, ananth.narayan@....com,
santosh.shukla@....com
Subject: Re: [PATCH v2 0/3] perf mem amd: Fix few logic bugs
On Wed, Jun 14, 2023 at 10:17 PM Ravi Bangoria <ravi.bangoria@....com> wrote:
>
> Recent PMU refactoring changes[1] introduced a notion of core vs other
> PMUs and made perf mem/c2c code depend only on core PMUs, which is
> logically wrong for AMD as perf mem/c2c on AMD depends on IBS OP PMU,
> not the core PMU. Although user visible perf mem/c2c functionality is
> still working fine, internal code logic is wrong. Fix those.
>
> [1] https://lore.kernel.org/r/20230527072210.2900565-1-irogers@google.com
>
> v1: https://lore.kernel.org/r/20230613095506.547-1-ravi.bangoria@amd.com
> v1->v2:
> - Patch #2 of last version is already picked up by Arnaldo. So skip it.
> - Scan all PMUs unconditionally in perf mem code instead of making it
> conditional on arch.
>
> Ravi Bangoria (3):
> perf pmus: Describe semantics of 'core_pmus' and 'other_pmus'
> perf mem amd: Fix perf_pmus__num_mem_pmus()
> perf mem: Scan all PMUs instead of just core ones
For the series:
Reviewed-by: Ian Rogers <irogers@...gle.com>
just a nit in a comment on the 2nd patch.
Thanks,
Ian
>
> tools/perf/arch/x86/util/pmu.c | 12 ++++++++++++
> tools/perf/util/mem-events.c | 13 +++++++++----
> tools/perf/util/pmus.c | 17 ++++++++++++++++-
> 3 files changed, 37 insertions(+), 5 deletions(-)
>
> --
> 2.40.1
>
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