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Message-ID: <2437bda9-bbdb-ad80-7201-1e16e1388890@linaro.org>
Date: Fri, 16 Jun 2023 12:45:09 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Eric Lin <eric.lin@...ive.com>, conor@...nel.org,
robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
palmer@...belt.com, paul.walmsley@...ive.com,
aou@...s.berkeley.edu, maz@...nel.org, chenhuacai@...nel.org,
baolu.lu@...ux.intel.com, will@...nel.org,
kan.liang@...ux.intel.com, nnac123@...ux.ibm.com,
pierre.gondois@....com, huangguangbin2@...wei.com, jgross@...e.com,
chao.gao@...el.com, maobibo@...ngson.cn,
linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, dslin1010@...il.com
Cc: Zong Li <zong.li@...ive.com>, Nick Hu <nick.hu@...ive.com>
Subject: Re: [PATCH 3/3] dt-bindings: riscv: sifive: Add SiFive Private L2
cache controller
On 16/06/2023 08:32, Eric Lin wrote:
> This add YAML DT binding documentation for SiFive Private L2
> cache controller
>
> Signed-off-by: Eric Lin <eric.lin@...ive.com>
> Reviewed-by: Zong Li <zong.li@...ive.com>
> Reviewed-by: Nick Hu <nick.hu@...ive.com>
> ---
> .../bindings/riscv/sifive,pL2Cache0.yaml | 81 +++++++++++++++++++
> 1 file changed, 81 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/riscv/sifive,pL2Cache0.yaml
>
> diff --git a/Documentation/devicetree/bindings/riscv/sifive,pL2Cache0.yaml b/Documentation/devicetree/bindings/riscv/sifive,pL2Cache0.yaml
> new file mode 100644
> index 000000000000..b5d8d4a39dde
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/riscv/sifive,pL2Cache0.yaml
> @@ -0,0 +1,81 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +# Copyright (C) 2023 SiFive, Inc.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/riscv/sifive,pL2Cache0.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: SiFive Private L2 Cache Controller
> +
> +maintainers:
> + - Greentime Hu <greentime.hu@...ive.com>
> + - Eric Lin <eric.lin@...ive.com>
> +
> +description:
> + The SiFive Private L2 Cache Controller is per hart and communicates with both the upstream
> + L1 caches and downstream L3 cache or memory, enabling a high-performance cache subsystem.
> + All the properties in ePAPR/DeviceTree specification applies for this platform.
Drop the last sentence. Why specification would not apply?
> +
> +allOf:
> + - $ref: /schemas/cache-controller.yaml#
> +
> +select:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - sifive,pL2Cache0
> + - sifive,pL2Cache
> +
> + required:
> + - compatible
> +
> +properties:
> + compatible:
> + items:
You have only one item, so no need for items... unless you just missed
proper fallback.
> + - enum:
> + - sifive,pL2Cache0
> + - sifive,pL2Cache1
What is "0" and "1" here? What do these compatibles represent? Why they
do not have any SoC related part?
> +
> + cache-block-size:
> + const: 64
> +
> + cache-level:
> + const: 2
> +
> + cache-sets:
> + const: 512
> +
> + cache-size:
> + const: 262144
Are you sure? So all private L2 cache controllers will have fixed size
of cache?
> +
> + cache-unified: true
> +
> + reg:
> + maxItems: 1
> +
> + next-level-cache: true
> +
> +additionalProperties: false
> +
> +required:
required: goes before additionalProperties:.
Best regards,
Krzysztof
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