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Message-ID: <20230618-tameness-crescent-d09ffa8ed4c0@spud>
Date: Sun, 18 Jun 2023 22:01:03 +0100
From: Conor Dooley <conor@...nel.org>
To: Jisheng Zhang <jszhang@...nel.org>
Cc: Thomas Gleixner <tglx@...utronix.de>,
Marc Zyngier <maz@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Albert Ou <aou@...s.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Conor Dooley <conor.dooley@...rochip.com>,
Guo Ren <guoren@...nel.org>, Fu Wei <wefu@...hat.com>,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
linux-riscv@...ts.infradead.org, arnd@...db.de
Subject: Re: [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support
On Mon, Jun 19, 2023 at 12:25:54AM +0800, Jisheng Zhang wrote:
> On Sat, Jun 17, 2023 at 07:20:43PM +0100, Conor Dooley wrote:
> > Going forward, who is going to pick up the patches and send the PRs to
> > Arnd? I wrote a document that should be in v6.5 about SoC tree
>
> Here is what I thought:
> From next development window,
>
> If we see a heavy development window, IOW, the patches size is big, I
> will take the job of picking up patches and sending out PRs.
>
> Once the development calms down, the patches size is trivial, I will
> explictly send request to you by repling the patches to ask your help
> to directly take the patches and send PRs.
The thing with this, is you don't really know in advance if the window
is going to be busy or not - you could end up getting a bunch of trivial
stuff pop up at a later -rc etc. I'd rather patches that ready to be
picked up didn't end up sitting un-applied on the list, until you figure
whether there has been enough to justify a PR or not.
If there is only one or two, you can always send the PR as a series of
patches, rather than creating a tag etc.
> Any comments are appreciated.
Could you please add a git tree to the MAINTAINERS entry & get it added
to linux-next? You should probably add another X: line to the MISC SOC
SUPPORT entry in the same patch.
Also, RISC-V is give-or-take clean for dtbs_check w/ W=1, please keep it
that way! I do keep an eye on it in linux-next, so if your tree is added
there, I'll at least see if changes in other parts of the kernel cause
warnings to spring up.
> > submaintainer stuff that is worth reading:
> > https://lore.kernel.org/all/20230606-escapable-stuffed-7ca5033e7741@wendy/
>
> The handbook is a wonderful document, thank you!
:)
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