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Message-ID: <20230620-catcher-jaybird-945d26a4f642@spud>
Date:   Tue, 20 Jun 2023 23:52:46 +0100
From:   Conor Dooley <conor@...nel.org>
To:     Jisheng Zhang <jszhang@...nel.org>
Cc:     Thomas Gleixner <tglx@...utronix.de>,
        Marc Zyngier <maz@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Palmer Dabbelt <palmer@...belt.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Daniel Lezcano <daniel.lezcano@...aro.org>,
        Conor Dooley <conor.dooley@...rochip.com>,
        Guo Ren <guoren@...nel.org>, Fu Wei <wefu@...hat.com>,
        linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
        linux-riscv@...ts.infradead.org, arnd@...db.de
Subject: Re: [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support

On Mon, Jun 19, 2023 at 12:25:54AM +0800, Jisheng Zhang wrote:
> On Sat, Jun 17, 2023 at 07:20:43PM +0100, Conor Dooley wrote:
> > From: Conor Dooley <conor.dooley@...rochip.com>

> > I'll send it to Arnd as a "RISC-V Devicetrees for v6.5 Part 2" once it
> > has been in linux-next for a day or two.
> 
> Thank you so much for helping the PR this time.

Just FYI, since I think only I get the notif emails, Arnd has merged it:
https://git.kernel.org/soc/soc/c/c9a5aa0e53d0

Cheers,
Conor.

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