linux-kernel - Re: [PATCH] perf vendor events arm64: Add AmpereOne core pmu events

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Message-ID: <76bb2e47-ce44-76ae-838e-53279047084d@oracle.com>
Date:   Wed, 21 Jun 2023 12:10:31 -0500
From:   Dave Kleikamp <dave.kleikamp@...cle.com>
To:     Ilkka Koskinen <ilkka@...amperecomputing.com>,
        John Garry <john.g.garry@...cle.com>,
        Will Deacon <will@...nel.org>,
        James Clark <james.clark@....com>,
        Mike Leach <mike.leach@...aro.org>,
        Leo Yan <leo.yan@...aro.org>
Cc:     Peter Zijlstra <peterz@...radead.org>,
        Ingo Molnar <mingo@...hat.com>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Jiri Olsa <jolsa@...nel.org>,
        Namhyung Kim <namhyung@...nel.org>,
        Ian Rogers <irogers@...gle.com>,
        Adrian Hunter <adrian.hunter@...el.com>,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-perf-users@...r.kernel.org
Subject: Re: [PATCH] perf vendor events arm64: Add AmpereOne core pmu events

On 4/27/23 5:32PM, Ilkka Koskinen wrote:
> Add JSON files for AmpereOne core PMU events.
> 
> Signed-off-by: Doug Rady <dcrady@...amperecomputing.com>
> Signed-off-by: Ilkka Koskinen <ilkka@...amperecomputing.com>
> ---

   CLIP

> diff --git a/tools/perf/pmu-events/arch/arm64/ampere/ampereone/cache.json b/tools/perf/pmu-events/arch/arm64/ampere/ampereone/cache.json
> new file mode 100644
> index 000000000000..fc0633054211
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/arm64/ampere/ampereone/cache.json
> @@ -0,0 +1,104 @@
> +[
> +    {
> +        "ArchStdEvent": "L1D_CACHE_RD"
> +    },
> +    {
> +        "ArchStdEvent": "L1D_CACHE_WR"
> +    },
> +    {
> +        "ArchStdEvent": "L1D_CACHE_REFILL_RD"
> +    },
> +    {
> +        "ArchStdEvent": "L1D_CACHE_INVAL"
> +    },
> +    {
> +        "ArchStdEvent": "L1D_TLB_REFILL_RD"
> +    },
> +    {
> +        "ArchStdEvent": "L1D_TLB_REFILL_WR"
> +    },
> +    {
> +        "ArchStdEvent": "L2D_CACHE_RD"
> +    },
> +    {
> +        "ArchStdEvent": "L2D_CACHE_WR"
> +    },
> +    {
> +        "ArchStdEvent": "L2D_CACHE_REFILL_RD"
> +    },
> +    {
> +        "ArchStdEvent": "L2D_CACHE_REFILL_WR"
> +    },
> +    {
> +        "ArchStdEvent": "L2D_CACHE_WB_VICTIM"
> +    },
> +    {
> +        "ArchStdEvent": "L2D_CACHE_WB_CLEAN"
> +    },
> +    {
> +        "ArchStdEvent": "L2D_CACHE_INVAL"
> +    },
> +    {
> +        "ArchStdEvent": "L1I_CACHE_REFILL"
> +    },
> +    {
> +        "ArchStdEvent": "L1I_TLB_REFILL"
> +    },
> +    {
> +        "ArchStdEvent": "L1D_CACHE_REFILL"
> +    },
> +    {
> +        "ArchStdEvent": "L1D_CACHE"
> +    },
> +    {
> +        "ArchStdEvent": "L1D_TLB_REFILL"
> +    },
> +    {
> +        "ArchStdEvent": "L1I_CACHE"
> +    },
> +    {
> +        "ArchStdEvent": "L2D_CACHE"
> +    },
> +    {
> +        "ArchStdEvent": "L2D_CACHE_REFILL"
> +    },
> +    {
> +        "ArchStdEvent": "L2D_CACHE_WB"
> +    },
> +    {
> +        "ArchStdEvent": "L1D_TLB"
> +    },
> +    {
> +        "ArchStdEvent": "L1I_TLB"
> +    },
> +    {
> +        "ArchStdEvent": "L2D_TLB_REFILL"
> +    },
> +    {
> +        "ArchStdEvent": "L2I_TLB_REFILL"
> +    },
> +    {
> +        "ArchStdEvent": "L2D_TLB"
> +    },
> +    {
> +        "ArchStdEvent": "L2I_TLB"
> +    },
> +    {
> +        "ArchStdEvent": "DTLB_WALK"
> +    },
> +    {
> +        "ArchStdEvent": "ITLB_WALK"
> +    },
> +    {
> +        "ArchStdEvent": "L1D_CACHE_LMISS_RD"
> +    },
> +    {
> +        "ArchStdEvent": "L1D_CACHE_LMISS"

L1D_CACHE_LMISS is not defined anywhere.

> +    },
> +    {
> +        "ArchStdEvent": "L1I_CACHE_LMISS"
> +    },
> +    {
> +        "ArchStdEvent": "L2D_CACHE_LMISS_RD"
> +    }
> +]