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Message-ID: <e8ad583-9650-2ad5-5447-a95ac9fb686a@os.amperecomputing.com>
Date: Wed, 21 Jun 2023 20:27:40 -0700 (PDT)
From: Ilkka Koskinen <ilkka@...amperecomputing.com>
To: Dave Kleikamp <dave.kleikamp@...cle.com>
cc: Ilkka Koskinen <ilkka@...amperecomputing.com>,
John Garry <john.g.garry@...cle.com>,
Will Deacon <will@...nel.org>,
James Clark <james.clark@....com>,
Mike Leach <mike.leach@...aro.org>,
Leo Yan <leo.yan@...aro.org>,
Peter Zijlstra <peterz@...radead.org>,
Ingo Molnar <mingo@...hat.com>,
Arnaldo Carvalho de Melo <acme@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Jiri Olsa <jolsa@...nel.org>,
Namhyung Kim <namhyung@...nel.org>,
Ian Rogers <irogers@...gle.com>,
Adrian Hunter <adrian.hunter@...el.com>,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-perf-users@...r.kernel.org
Subject: Re: [PATCH] perf vendor events arm64: Add AmpereOne core pmu
events
Hi Dave,
On Wed, 21 Jun 2023, Dave Kleikamp wrote:
> On 4/27/23 5:32PM, Ilkka Koskinen wrote:
>> Add JSON files for AmpereOne core PMU events.
>>
>> Signed-off-by: Doug Rady <dcrady@...amperecomputing.com>
>> Signed-off-by: Ilkka Koskinen <ilkka@...amperecomputing.com>
>> ---
>
> CLIP
>
>> diff --git a/tools/perf/pmu-events/arch/arm64/ampere/ampereone/cache.json
>> b/tools/perf/pmu-events/arch/arm64/ampere/ampereone/cache.json
>> new file mode 100644
>> index 000000000000..fc0633054211
>> --- /dev/null
>> +++ b/tools/perf/pmu-events/arch/arm64/ampere/ampereone/cache.json
>> @@ -0,0 +1,104 @@
>> +[
>> + {
>> + "ArchStdEvent": "L1D_CACHE_RD"
>> + },
....
>> + {
>> + "ArchStdEvent": "L1D_CACHE_LMISS_RD"
>> + },
>> + {
>> + "ArchStdEvent": "L1D_CACHE_LMISS"
>
> L1D_CACHE_LMISS is not defined anywhere.
Good catch! I must have thought the python script would at least print a
warning of missing event as I compared the build logs with and without the
patch. I can prepare a fix for this and submit with another couple of
patches. I'm hoping to be able to do that by the beginning of next week.
Cheers, Ilkka
>
>> + },
>> + {
>> + "ArchStdEvent": "L1I_CACHE_LMISS"
>> + },
>> + {
>> + "ArchStdEvent": "L2D_CACHE_LMISS_RD"
>> + }
>> +]
>
>
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