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Date:   Thu, 22 Jun 2023 09:37:45 +0200
From:   Lorenzo Pieralisi <lpieralisi@...nel.org>
To:     alberto.dassatti@...g-vd.ch,
        Rick Wertenbroek <rick.wertenbroek@...il.com>
Cc:     Lorenzo Pieralisi <lpieralisi@...nel.org>, xxm@...k-chips.com,
        dlemoal@...nel.org, Shawn Lin <shawn.lin@...k-chips.com>,
        Krzysztof WilczyƄski <kw@...ux.com>,
        Rob Herring <robh@...nel.org>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Heiko Stuebner <heiko@...ech.de>,
        Brian Norris <briannorris@...omium.org>,
        Caleb Connolly <kc@...tmarketos.org>,
        Johan Jonker <jbx6244@...il.com>,
        Corentin Labbe <clabbe@...libre.com>,
        Hugh Cole-Baker <sigmaris@...il.com>,
        Arnaud Ferraris <arnaud.ferraris@...labora.com>,
        Judy Hsiao <judyhsiao@...omium.org>, linux-pci@...r.kernel.org,
        linux-rockchip@...ts.infradead.org, devicetree@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: (subset) [PATCH v5 00/11] PCI: rockchip: Fix RK3399 PCIe endpoint controller driver

On Tue, 18 Apr 2023 09:46:47 +0200, Rick Wertenbroek wrote:
> This is a series of patches that fixes the PCIe endpoint controller driver
> for the Rockchip RK3399 SoC. The driver was introduced in commit
> cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller")
> The original driver had issues and would not allow for the RK3399 to
> operate in PCIe endpoint mode correctly. This patch series fixes that so
> that the PCIe core controller of the RK3399 SoC can now act as a PCIe
> endpoint. This is v5 of the patch series and addresses the comments received
> during the review of the v4 [1]. The changes to the v4 are minor and none of
> them change the logic of the driver.
> 
> [...]

Applied to controller/rockchip, thanks!

[01/11] PCI: rockchip: Remove writes to unused registers
        https://git.kernel.org/pci/pci/c/92a9c57c325d
[02/11] PCI: rockchip: Write PCI Device ID to correct register
        https://git.kernel.org/pci/pci/c/1f1c42ece18d
[03/11] PCI: rockchip: Assert PCI Configuration Enable bit after probe
        https://git.kernel.org/pci/pci/c/f397fd4ac1fa
[04/11] PCI: rockchip: Add poll and timeout to wait for PHY PLLs to be locked
        https://git.kernel.org/pci/pci/c/9dd3c7c4c8c3
[06/11] dt-bindings: PCI: Update the RK3399 example to a valid one
        https://git.kernel.org/pci/pci/c/21a2960d5ea2
[07/11] PCI: rockchip: Fix legacy IRQ generation for RK3399 PCIe endpoint core
        https://git.kernel.org/pci/pci/c/166e89d99dd8
[08/11] PCI: rockchip: Fix window mapping and address translation for endpoint
        https://git.kernel.org/pci/pci/c/dc73ed0f1b8b
[09/11] PCI: rockchip: Use u32 variable to access 32-bit registers
        https://git.kernel.org/pci/pci/c/8962b2cb3911
[10/11] PCI: rockchip: Don't advertise MSI-X in PCIe capabilities
        https://git.kernel.org/pci/pci/c/a52587e0bee1
[11/11] PCI: rockchip: Set address alignment for endpoint mode
        https://git.kernel.org/pci/pci/c/7e6689b34a81

Thanks,
Lorenzo

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