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Message-ID: <50db7ca9-6e5f-2f9a-61af-bb5b09898b72@amd.com>
Date: Thu, 22 Jun 2023 09:42:01 -0500
From: Terry Bowman <Terry.Bowman@....com>
To: Jonathan Cameron <Jonathan.Cameron@...wei.com>
Cc: alison.schofield@...el.com, vishal.l.verma@...el.com,
ira.weiny@...el.com, bwidawsk@...nel.org, dan.j.williams@...el.com,
dave.jiang@...el.com, linux-cxl@...r.kernel.org, rrichter@....com,
linux-kernel@...r.kernel.org, bhelgaas@...gle.com
Subject: Re: [PATCH v6 23/27] cxl/pci: Map RCH downstream AER registers for
logging protocol errors
Hi Jonathan,
Thanks for the reviews.
On 6/22/23 08:16, Jonathan Cameron wrote:
> On Wed, 21 Jun 2023 22:51:22 -0500
> Terry Bowman <terry.bowman@....com> wrote:
>
>> The restricted CXL host (RCH) error handler will log protocol errors
>> using AER and RAS status registers. The AER and RAS registers need
>> to be virtually memory mapped before enabling interrupts. Update
>> __devm_cxl_add_dport() to include RCH RAS and AER mapping.
>>
>> Add 'struct cxl_regs' to 'struct cxl_dport' for saving a unique copy of
>> the RCH downstream port's mapped registers.
>
> Copy of the address at which they are mapped, not the registers.
> Probably worth tweaking description to make that clearer.
>
Good point. I'll change to the following:
"Add 'struct cxl_regs' to 'struct cxl_dport' for saving a pointer to
the RCH downstream port's AER and RAS registers."
Regards,
Terry
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