linux-kernel - Re: [RESEND v6 5/8] arm64: dts: qcom: sc7280: Add LPASS PIL node

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <c875c617-25d2-04d8-0ab7-f7e8380348c9@quicinc.com>
Date:   Mon, 26 Jun 2023 16:37:04 +0530
From:   Mohammad Rafi Shaik <quic_mohs@...cinc.com>
To:     Konrad Dybcio <konrad.dybcio@...aro.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <swboyd@...omium.org>,
        <andersson@...nel.org>, <broonie@...nel.org>, <agross@...nel.org>
CC:     <robh+dt@...nel.org>, <linux-arm-msm@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <quic_rohkumar@...cinc.com>, <srinivas.kandagatla@...aro.org>,
        <dianders@...omium.org>, <judyhsiao@...omium.org>,
        <quic_visr@...cinc.com>,
        Srinivasa Rao Mandadapu <quic_srivasam@...cinc.com>
Subject: Re: [RESEND v6 5/8] arm64: dts: qcom: sc7280: Add LPASS PIL node


On 6/16/2023 4:55 PM, Konrad Dybcio wrote:
> On 16.06.2023 12:35, Mohammad Rafi Shaik wrote:
>> From: Srinivasa Rao Mandadapu <quic_srivasam@...cinc.com>
>>
>> Add LPASS PIL node for sc7280 based audioreach platforms.
>>
>> Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@...cinc.com>
>> Signed-off-by: Mohammad Rafi Shaik <quic_mohs@...cinc.com>
>> ---
> The node should reside in the SoC DTSI, ideally the bindings should
> be compatible with the PAS setup to the point where only a compatible
> swap is needed..
>
> Konrad
Thanks for comment,

The base SOC DTSI file already has an entry with the same physical base 
address which is using for ADSP BYPASS solution.
For Audioreach solution required the same base address for the 
remoteproc device tree node.

Will create a new common dtsi file for Audioreach as suggested by you in 
previous patch and add this in that common dtsi file.

Please confirm is it okay ?

Rafi.

>>   .../sc7280-herobrine-audioreach-wcd9385.dtsi  | 90 +++++++++++++++++++
>>   1 file changed, 90 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
>> index 95d3aa08ebde..9daea1b25656 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
>> @@ -7,6 +7,8 @@
>>    */
>>   
>>   #include <dt-bindings/sound/qcom,q6afe.h>
>> +#include <dt-bindings/clock/qcom,lpass-sc7280.h>
>> +#include <dt-bindings/soc/qcom,gpr.h>
>>   
>>   /{
>>   	/* BOARD-SPECIFIC TOP LEVEL NODES */
>> @@ -105,4 +107,92 @@ platform {
>>   			};
>>   		};
>>   	};
>> +
>> +	remoteproc_adsp: remoteproc@...0000 {
>> +		compatible = "qcom,sc7280-adsp-pil";
>> +		reg = <0 0x03000000 0 0x5000>, <0 0x0355b000 0 0x10>;
>> +		reg-names = "qdsp6ss_base", "lpass_efuse";
>> +
>> +		interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
>> +				      <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
>> +				      <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
>> +				      <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
>> +				      <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
>> +				      <&adsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
>> +
>> +		interrupt-names = "wdog", "fatal", "ready",
>> +				  "handover", "stop-ack",
>> +				  "shutdown-ack";
>> +
>> +		qcom,qmp = <&aoss_qmp>;
>> +
>> +		clocks = <&rpmhcc RPMH_CXO_CLK>,
>> +			 <&gcc GCC_CFG_NOC_LPASS_CLK>;
>> +		clock-names = "xo", "gcc_cfg_noc_lpass";
>> +
>> +		iommus = <&apps_smmu 0x1800 0x0>;
>> +
>> +		power-domains =	<&rpmhpd SC7280_CX>;
>> +		power-domain-names = "cx";
>> +
>> +		required-opps = <&rpmhpd_opp_nom>;
>> +
>> +		resets = <&pdc_reset PDC_AUDIO_SYNC_RESET>,
>> +			 <&aoss_reset AOSS_CC_LPASS_RESTART>;
>> +		reset-names =  "pdc_sync", "cc_lpass";
>> +
>> +		qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x8000 0x13000>;
>> +
>> +		memory-region = <&adsp_mem>;
>> +
>> +		qcom,smem-states = <&adsp_smp2p_out 0>;
>> +		qcom,smem-state-names = "stop";
>> +
>> +		glink-edge {
>> +			interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
>> +					      IPCC_MPROC_SIGNAL_GLINK_QMP
>> +					      IRQ_TYPE_EDGE_RISING>;
>> +
>> +			mboxes = <&ipcc IPCC_CLIENT_LPASS
>> +				 IPCC_MPROC_SIGNAL_GLINK_QMP>;
>> +
>> +			label = "lpass";
>> +			qcom,remote-pid = <2>;
>> +
>> +			gpr {
>> +				compatible = "qcom,gpr";
>> +				qcom,glink-channels = "adsp_apps";
>> +				qcom,domain = <GPR_DOMAIN_ID_ADSP>;
>> +				qcom,intents = <512 20>;
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +
>> +				q6apm: service@1 {
>> +					compatible = "qcom,q6apm";
>> +					reg = <GPR_APM_MODULE_IID>;
>> +					#sound-dai-cells = <0>;
>> +
>> +					q6apmdai: dais {
>> +						compatible = "qcom,q6apm-dais";
>> +						iommus = <&apps_smmu 0x1801 0x0>;
>> +					};
>> +
>> +					q6apmbedai: bedais {
>> +						compatible = "qcom,q6apm-lpass-dais";
>> +						#sound-dai-cells = <1>;
>> +					};
>> +				};
>> +
>> +				q6prm: service@2 {
>> +					compatible = "qcom,q6prm";
>> +					reg = <GPR_PRM_MODULE_IID>;
>> +
>> +					q6prmcc: clock-controller {
>> +						compatible = "qcom,q6prm-lpass-clocks";
>> +						#clock-cells = <2>;
>> +					};
>> +				};
>> +			};
>> +		};
>> +	};
>>   };