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Message-ID: <tcwgwwyx5lvoowp2bxkaemfp7eefbvmfzwprcml7wmtrwadxtm@et2ofo64cru2>
Date: Tue, 27 Jun 2023 16:15:12 +0300
From: Serge Semin <fancer.lancer@...il.com>
To: Sebastian Reichel <sebastian.reichel@...labora.com>
Cc: linux-pci@...r.kernel.org, linux-rockchip@...ts.infradead.org,
Jingoo Han <jingoohan1@...il.com>,
Gustavo Pimentel <gustavo.pimentel@...opsys.com>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof WilczyĆski <kw@...ux.com>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Heiko Stuebner <heiko@...ech.de>,
Shawn Lin <shawn.lin@...k-chips.com>,
Simon Xue <xxm@...k-chips.com>, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
kernel@...labora.com
Subject: Re: [PATCH v1 3/4] dt-bindings: PCI: dwc: rockchip: Update for RK3588
On Fri, Jun 16, 2023 at 07:00:21PM +0200, Sebastian Reichel wrote:
> The PCIe 2.0 controllers on RK3588 need one additional clock,
> one additional reset line and one for ranges entry.
Just a nitpick: it would be perfect to have these new items evaluated
compatible-string conditionally. Anyway:
Reviewed-by: Serge Semin <fancer.lancer@...il.com>
-Serge(y)
>
> Signed-off-by: Sebastian Reichel <sebastian.reichel@...labora.com>
> ---
> .../bindings/pci/rockchip-dw-pcie.yaml | 16 +++++++++++++---
> 1 file changed, 13 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
> index bf81d306cc80..7897af0ec297 100644
> --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
> @@ -41,20 +41,24 @@ properties:
> - const: config
>
> clocks:
> + minItems: 5
> items:
> - description: AHB clock for PCIe master
> - description: AHB clock for PCIe slave
> - description: AHB clock for PCIe dbi
> - description: APB clock for PCIe
> - description: Auxiliary clock for PCIe
> + - description: PIPE clock
>
> clock-names:
> + minItems: 5
> items:
> - const: aclk_mst
> - const: aclk_slv
> - const: aclk_dbi
> - const: pclk
> - const: aux
> + - const: pipe
>
> interrupts:
> maxItems: 5
> @@ -97,13 +101,19 @@ properties:
> maxItems: 1
>
> ranges:
> - maxItems: 2
> + minItems: 2
> + maxItems: 3
>
> resets:
> - maxItems: 1
> + minItems: 1
> + maxItems: 2
>
> reset-names:
> - const: pipe
> + oneOf:
> + - const: pipe
> + - items:
> + - const: pwr
> + - const: pipe
>
> vpcie3v3-supply: true
>
> --
> 2.39.2
>
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