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Message-ID: <ca71fc1f-280e-19ff-ce0f-8befa29f45cd@gmail.com>
Date: Wed, 28 Jun 2023 12:25:16 +0800
From: Like Xu <like.xu.linux@...il.com>
To: Xiong Zhang <xiong.y.zhang@...el.com>,
Sean Christopherson <seanjc@...gle.com>
Cc: pbonzini@...hat.com, peterz@...radead.org,
kan.liang@...ux.intel.com, zhenyuw@...ux.intel.com,
zhiyuan.lv@...el.com, kvm list <kvm@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/4] perf/x86/intel: Get shared reg constraints first for
vLBR
On 16/6/2023 7:33 pm, Xiong Zhang wrote:
> When host has per cpu pinned LBR event and guest use LBR also, host
> couldn't get correct LBR data, as the physical LBR is preempted by
> guest.
>
> The rule for multi events sharing LBR is defined in
> __intel_shared_reg_get_constraints(), but guest vLBR event skips this
> function, so even if host has per cpu pinned LBR event, guest vLBR event
> could get constraints successfully and make vlbr_exclude_host returns true,
> finally host couldn't enable LBR in intel_pmu_lbr_enable_all().
Although it goes against the "per cpu pinned LBR event" priority expectation,
the order is intentionally specified. For two reasons:
- vlbr uses the fake event mechanism in its implementation, a presence similar to
BTS event, thus the question here is whether we can get the per cpu pinned BTS
event to work as expected;
- this change should not be applied first before KVM has done a good job
of making guest lbr and other lbr events coexist correctly;
In treating vlbr event as an ordinary perf_event behind a guest counter that
is expected to comply equally with the scheduling rules of host perf, the first
thing we need to address is how a guest counter should continue to function
during the time when the backend event is preempted by a higher priority one.
>
> This commit move intel_vlbr_constraints() behind
> intel_shared_regs_constraints(), guest vLBR event will use LBR also and it
> should get LBR resource through intel_shared_regs_constraints().
>
> Fixes: 097e4311cda9 ("perf/x86: Add constraint to create guest LBR event without hw counter")
> Signed-off-by: Xiong Zhang <xiong.y.zhang@...el.com>
> ---
> arch/x86/events/intel/core.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index 6fd3cd97a6ac..2e27a69e9725 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -3347,15 +3347,15 @@ __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
> {
> struct event_constraint *c;
>
> - c = intel_vlbr_constraints(event);
> + c = intel_bts_constraints(event);
> if (c)
> return c;
>
> - c = intel_bts_constraints(event);
> + c = intel_shared_regs_constraints(cpuc, event);
> if (c)
> return c;
>
> - c = intel_shared_regs_constraints(cpuc, event);
> + c = intel_vlbr_constraints(event);
> if (c)
> return c;
>
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