linux-kernel - Re: [PATCH v3 0/9] Introduce SMT level and add PowerPC support

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Date:   Fri, 30 Jun 2023 15:41:24 +0200
From:   Laurent Dufour <ldufour@...ux.ibm.com>
To:     Sachin Sant <sachinp@...ux.ibm.com>
Cc:     linuxppc-dev <linuxppc-dev@...ts.ozlabs.org>,
        linux-arch@...r.kernel.org, dave.hansen@...ux.intel.com,
        open list <linux-kernel@...r.kernel.org>,
        Ingo Molnar <mingo@...hat.com>, bp@...en8.de,
        npiggin@...il.com, tglx@...utronix.de
Subject: Re: [PATCH v3 0/9] Introduce SMT level and add PowerPC support



Le 30/06/2023 à 15:32, Sachin Sant a écrit :
> 
> 
>> On 29-Jun-2023, at 8:01 PM, Laurent Dufour <ldufour@...ux.ibm.com> wrote:
>>
>> I'm taking over the series Michael sent previously [1] which is smartly
>> reviewing the initial series I sent [2].  This series is addressing the
>> comments sent by Thomas and me on the Michael's one.
>>
>> Here is a short introduction to the issue this series is addressing:
>>
>> When a new CPU is added, the kernel is activating all its threads. This
>> leads to weird, but functional, result when adding CPU on a SMT 4 system
>> for instance.
>>
>> Here the newly added CPU 1 has 8 threads while the other one has 4 threads
>> active (system has been booted with the 'smt-enabled=4' kernel option):
>>
>> ltcden3-lp12:~ # ppc64_cpu --info
>> Core   0:    0*    1*    2*    3*    4     5     6     7
>> Core   1:    8*    9*   10*   11*   12*   13*   14*   15*
>>
>> This mixed SMT level may confused end users and/or some applications.
>>
>> There is no SMT level recorded in the kernel (common code), neither in user
>> space, as far as I know. Such a level is helpful when adding new CPU or
>> when optimizing the energy efficiency (when reactivating CPUs).
>>
>> When SMP and HOTPLUG_SMT are defined, this series is adding a new SMT level
>> (cpu_smt_num_threads) and few callbacks allowing the architecture code to
>> fine control this value, setting a max and a "at boot" level, and
>> controling whether a thread should be onlined or not.
>>
>> v3:
>>   Fix a build error in the patch 6/9
> 
> Successfully tested the V3 version on a Power10 LPAR. Add/remove of
> processor core worked correctly, preserving the SMT level (on a kernel
> booted with smt-enabled= parameter)
> 
> Laurent (Thanks!) also provided a patch to update the ppc64_cpu &
> lparstat utility. With patched ppc64_cpu utility verified that SMT level
> changed at runtime was preserved across processor core add (on
> a kernel booted without smt-enabled= parameter)
> 
> Based on these test results
> 
> Tested-by: Sachin Sant <sachinp@...ux.ibm.com>

Thanks a lot, Sachin!

Once this series is accepted, I'll send the series to update ppc64_cpu.