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Message-Id: <168822630425.22742.10407688185048619244.git-patchwork-notify@kernel.org>
Date:   Sat, 01 Jul 2023 15:45:04 +0000
From:   patchwork-bot+linux-riscv@...nel.org
To:     Xingyu Wu <xingyu.wu@...rfivetech.com>
Cc:     linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
        mturquette@...libre.com, sboyd@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, p.zabel@...gutronix.de,
        conor@...nel.org, kernel@...il.dk, robh+dt@...nel.org,
        paul.walmsley@...ive.com, palmer@...belt.com,
        aou@...s.berkeley.edu, hal.feng@...rfivetech.com,
        linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org
Subject: Re: [PATCH v6 00/11] Add STG/ISP/VOUT clock and reset drivers for
 StarFive JH7110

Hello:

This series was applied to riscv/linux.git (fixes)
by Conor Dooley <conor.dooley@...rochip.com>:

On Thu, 18 May 2023 18:12:23 +0800 you wrote:
> This patch serises are base on the basic JH7110 SYSCRG/AONCRG
> drivers and add new partial clock drivers and reset supports
> about System-Top-Group(STG), Image-Signal-Process(ISP)
> and Video-Output(VOUT) for the StarFive JH7110 RISC-V SoC. These
> clocks and resets could be used by DMA, VIN and Display modules.
> 
> Patches 1 and 2 are about the System-Top-Group clock and reset
> generator(STGCRG) part. The first patch adds docunmentation to
> describe STG bindings, and the second patch adds clock driver to
> support STG clocks and resets as auxiliary device for JH7110.
> 
> [...]

Here is the summary with links:
  - [v6,01/11] dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator
    (no matching commit)
  - [v6,02/11] clk: starfive: Add StarFive JH7110 System-Top-Group clock driver
    (no matching commit)
  - [v6,03/11] dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator
    (no matching commit)
  - [v6,04/11] clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver
    (no matching commit)
  - [v6,05/11] dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator
    (no matching commit)
  - [v6,06/11] clk: starfive: Add StarFive JH7110 Video-Output clock driver
    (no matching commit)
  - [v6,07/11] MAINTAINERS: Update maintainer of JH71x0 clock drivers
    (no matching commit)
  - [v6,08/11] reset: starfive: jh7110: Add StarFive STG/ISP/VOUT resets support
    (no matching commit)
  - [v6,09/11] riscv: dts: starfive: jh7110: add pmu controller node
    https://git.kernel.org/riscv/c/6a887bcc4138
  - [v6,10/11] riscv: dts: starfive: jh7110: Add DVP and HDMI TX pixel external clocks
    (no matching commit)
  - [v6,11/11] riscv: dts: starfive: jh7110: Add STGCRG/ISPCRG/VOUTCRG nodes
    (no matching commit)

You are awesome, thank you!
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