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Message-ID: <4afd90d9-f1bd-f40d-1c79-50fef1406ab7@linaro.org>
Date: Tue, 4 Jul 2023 14:27:57 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Mark Brown <broonie@...nel.org>
Cc: William Qiu <william.qiu@...rfivetech.com>,
devicetree@...r.kernel.org, linux-spi@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Emil Renner Berthing <kernel@...il.dk>,
Linus Walleij <linus.walleij@...aro.org>
Subject: Re: [RESEND v1 2/2] riscv: dts: starfive: Add spi node for JH7110 SoC
On 04/07/2023 14:26, Mark Brown wrote:
> On Tue, Jul 04, 2023 at 11:39:29AM +0200, Krzysztof Kozlowski wrote:
>> On 04/07/2023 11:22, William Qiu wrote:
>>> Add spi node for JH7110 SoC.
>>>
>>> Co-developed-by: Xingyu Wu <xingyu.wu@...rfivetech.com>
>>
>> Missing SoB.
>
> It's fine not to have a signoff for the codeveloper of codeveloped
> patches, see case (a) for the DCO.
Also see:
"every Co-developed-by: must be immediately
followed by a Signed-off-by: of the associated co-author."
https://elixir.bootlin.com/linux/v6.4/source/Documentation/process/submitting-patches.rst#L467
Best regards,
Krzysztof
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