linux-kernel - Re: [RESEND v1 2/2] riscv: dts: starfive: Add spi node for JH7110 SoC

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <1e9dedc6-dee3-b65d-2823-0468fcb13193@starfivetech.com>
Date:   Wed, 5 Jul 2023 11:40:43 +0800
From:   William Qiu <william.qiu@...rfivetech.com>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
        <devicetree@...r.kernel.org>, <linux-spi@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <linux-riscv@...ts.infradead.org>
CC:     Mark Brown <broonie@...nel.org>, Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Emil Renner Berthing <kernel@...il.dk>,
        Linus Walleij <linus.walleij@...aro.org>
Subject: Re: [RESEND v1 2/2] riscv: dts: starfive: Add spi node for JH7110 SoC



On 2023/7/4 17:39, Krzysztof Kozlowski wrote:
> On 04/07/2023 11:22, William Qiu wrote:
>> Add spi node for JH7110 SoC.
>> 
>> Co-developed-by: Xingyu Wu <xingyu.wu@...rfivetech.com>
> 
> Missing SoB.
> 
It looks like that drop it is the best solution.
>> Signed-off-by: William Qiu <william.qiu@...rfivetech.com>
>> ---
>>  .../jh7110-starfive-visionfive-2.dtsi         | 52 ++++++++++
>>  arch/riscv/boot/dts/starfive/jh7110.dtsi      | 98 +++++++++++++++++++
>>  2 files changed, 150 insertions(+)
>> 
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> index 2a6d81609284..a066d2e399c4 100644
>> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> @@ -126,6 +126,20 @@ &i2c6 {
>>  	status = "okay";
>>  };
>> 
>> +&spi0 {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&spi0_pins>;
>> +	status = "okay";
>> +
>> +	spi_dev0: spi@0 {
>> +		compatible = "st,m25p80";
>> +		pl022,com-mode = <1>;
>> +		spi-max-frequency = <10000000>;
>> +		reg = <0>;
> 
> reg is always following compatible, not somewhere deep in properties.
> 
Will update.
>> +		status = "okay";
> 
> okay is by default
> 
Will drop.
>> +	};
>> +};
> 
> 
> Best regards,
> Krzysztof
> 
Thanks for taking time to review this patch series.