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Date:   Mon, 10 Jul 2023 15:01:52 +0000
From:   David Laight <David.Laight@...LAB.COM>
To:     'David Gow' <davidgow@...gle.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
        Dave Hansen <dave.hansen@...ux.intel.com>,
        "H . Peter Anvin" <hpa@...or.com>,
        "Noah Goldstein" <goldstein.w.n@...il.com>
CC:     "x86@...nel.org" <x86@...nel.org>,
        Geert Uytterhoeven <geert@...ux-m68k.org>,
        "linux-kselftest@...r.kernel.org" <linux-kselftest@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH] x86: checksum: Fix unaligned checksums on < i686

From: David Gow
> Sent: 04 July 2023 09:32
> 
> The checksum_32 code was originally written to only handle 2-byte
> aligned buffers, but was later extended to support arbitrary alignment.
> However, the non-PPro variant doesn't apply the carry before jumping to
> the 2- or 4-byte aligned versions, which clear CF.
....
> I also tested it on a real 486DX2, with the same results.

Which cpu does anyone really care about?

The unrolled 'adcl' loop is horrid on intel cpu between
(about) 'core' and 'haswell' because each u-op can only
have two inputs and adc needs 3 - so is 2 u-ops.
First fixed by summing to alternate registers.

On anything modern (well I've not checked some Atom based
servers) misaligned accesses are pretty near zero cost.
So it really isn't worth the tests that align data.

(I suspect it all got better a long time ago except
for transfers that cross cache-line boundaries, with
adc taking two cycles even that might be free.)

	David

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