linux-kernel - Re: [PATCH 0/2] Misc RISC-V timer driver improvements

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Date:   Tue, 11 Jul 2023 17:07:11 +0530
From:   Anup Patel <apatel@...tanamicro.com>
To:     Conor Dooley <conor.dooley@...rochip.com>
Cc:     Palmer Dabbelt <palmer@...belt.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Daniel Lezcano <daniel.lezcano@...aro.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Atish Patra <atishp@...shpatra.org>,
        Andrew Jones <ajones@...tanamicro.com>,
        Sunil V L <sunilvl@...tanamicro.com>,
        Conor Dooley <conor@...nel.org>,
        Anup Patel <anup@...infault.org>,
        linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 0/2] Misc RISC-V timer driver improvements

On Tue, Jul 11, 2023 at 4:51 PM Conor Dooley <conor.dooley@...rochip.com> wrote:
>
> On Mon, Jul 10, 2023 at 06:49:00PM +0530, Anup Patel wrote:
> > This series does two improvements to the RISC-V timer driver:
> > 1) Keep timer interrupt enable state in-sync with interrupt subsystem
> > 2) Increase rating of clock event device when Sstc is available
> >
> > These patches can also be found in the riscv_timer_imp_v1 branch at:
> > https://github.com/avpatel/linux.git
>
> Other than wondering why you opted for 450 (curiosity really), this
> stuff looks fine to me.

It is the same as the rating for clock_event_device used by ARM arch timer.
(Refer, __arch_timer_setup() in drivers/clocksource/arm_arch_timer.c)

>
> Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>
>
> Cheers,
> Conor.

Regards,
Anup