lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <597f53e0-5a5b-75a1-4054-253630a941f2@arm.com>
Date:   Tue, 11 Jul 2023 15:12:44 +0100
From:   James Clark <james.clark@....com>
To:     Anshuman Khandual <anshuman.khandual@....com>
Cc:     Peter Zijlstra <peterz@...radead.org>,
        Ingo Molnar <mingo@...hat.com>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Jiri Olsa <jolsa@...nel.org>,
        Namhyung Kim <namhyung@...nel.org>,
        Adrian Hunter <adrian.hunter@...el.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Borislav Petkov <bp@...en8.de>,
        Dave Hansen <dave.hansen@...ux.intel.com>, x86@...nel.org,
        "H. Peter Anvin" <hpa@...or.com>, Will Deacon <will@...nel.org>,
        Kan Liang <kan.liang@...ux.intel.com>,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-perf-users@...r.kernel.org, irogers@...gle.com
Subject: Re: [PATCH 1/4] arm_pmu: Add PERF_PMU_CAP_EXTENDED_HW_TYPE capability



On 11/07/2023 13:01, Anshuman Khandual wrote:
> 
> 
> On 7/10/23 17:51, James Clark wrote:
>> This capability gives us the ability to open PERF_TYPE_HARDWARE and
>> PERF_TYPE_HW_CACHE events on a specific PMU for free. All the
>> implementation is contained in the Perf core and tool code so no change
>> to the Arm PMU driver is needed.
>>
>> The following basic use case now results in Perf opening the event on
>> all PMUs rather than picking only one in an unpredictable way:
>>
>>   $ perf stat -e cycles -- taskset --cpu-list 0,1 stress -c 2
>>
>>    Performance counter stats for 'taskset --cpu-list 0,1 stress -c 2':
>>
>>          963279620      armv8_cortex_a57/cycles/                (99.19%)
>>          752745657      armv8_cortex_a53/cycles/                (94.80%)
>>
>> Fixes: 55bcf6ef314a ("perf: Extend PERF_TYPE_HARDWARE and PERF_TYPE_HW_CACHE")
>> Suggested-by: Ian Rogers <irogers@...gle.com>
>> Signed-off-by: James Clark <james.clark@....com>
>> ---
>>  drivers/perf/arm_pmu.c | 7 ++++++-
>>  1 file changed, 6 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c
>> index 277e29fbd504..d8844a9461a2 100644
>> --- a/drivers/perf/arm_pmu.c
>> +++ b/drivers/perf/arm_pmu.c
>> @@ -875,8 +875,13 @@ struct arm_pmu *armpmu_alloc(void)
>>  		 * configuration (e.g. big.LITTLE). This is not an uncore PMU,
>>  		 * and we have taken ctx sharing into account (e.g. with our
>>  		 * pmu::filter callback and pmu::event_init group validation).
>> +		 *
>> +		 * PERF_PMU_CAP_EXTENDED_HW_TYPE is required to open the legacy
> 
> s/legacy/generic ? These hardware events are still around.

True, I thought I saw it mentioned that way somewhere, but I can
probably just remove it altogether. PERF_TYPE_HARDWARE and
PERF_TYPE_HW_CACHE is enough.


> 
>> +		 * PERF_TYPE_HARDWARE and PERF_TYPE_HW_CACHE events on a
>> +		 * specific PMU.
>>  		 */
>> -		.capabilities	= PERF_PMU_CAP_HETEROGENEOUS_CPUS | PERF_PMU_CAP_EXTENDED_REGS,
>> +		.capabilities	= PERF_PMU_CAP_HETEROGENEOUS_CPUS | PERF_PMU_CAP_EXTENDED_REGS |
>> +				  PERF_PMU_CAP_EXTENDED_HW_TYPE,
>>  	};
>>  
>>  	pmu->attr_groups[ARMPMU_ATTR_GROUP_COMMON] =

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ