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Message-ID: <4c5b0534bc57045f4a5e63c2a3e4db8eda4f42ff.camel@intel.com>
Date: Wed, 12 Jul 2023 19:34:27 +0000
From: "Verma, Vishal L" <vishal.l.verma@...el.com>
To: "dan.carpenter@...aro.org" <dan.carpenter@...aro.org>
CC: "kernel-janitors@...r.kernel.org" <kernel-janitors@...r.kernel.org>,
"Jiang, Dave" <dave.jiang@...el.com>,
"Schofield, Alison" <alison.schofield@...el.com>,
"Jonathan.Cameron@...wei.com" <Jonathan.Cameron@...wei.com>,
"linux-cxl@...r.kernel.org" <linux-cxl@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"Williams, Dan J" <dan.j.williams@...el.com>,
"Weiny, Ira" <ira.weiny@...el.com>,
"bwidawsk@...nel.org" <bwidawsk@...nel.org>
Subject: Re: [PATCH] cxl/mem: Fix a double shift bug
On Mon, 2023-07-03 at 17:17 +0300, Dan Carpenter wrote:
> The CXL_FW_CANCEL macro is used with set/test_bit() so it should be a
> bit number and not the shifted value. The original code is the
> equivalent of using BIT(BIT(0)) so it's 0x2 instead of 0x1. This has
> no effect on runtime because it's done consistently and nothing else
> was using the 0x2 bit.
>
> Fixes: 9521875bbe00 ("cxl: add a firmware update mechanism using the sysfs firmware loader")
> Signed-off-by: Dan Carpenter <dan.carpenter@...aro.org>
Reviewed-by: Vishal Verma <vishal.l.verma@...el.com>
> ---
> drivers/cxl/cxlmem.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> index 79e99c873ca2..499113328586 100644
> --- a/drivers/cxl/cxlmem.h
> +++ b/drivers/cxl/cxlmem.h
> @@ -323,7 +323,7 @@ struct cxl_mbox_activate_fw {
>
> /* FW state bits */
> #define CXL_FW_STATE_BITS 32
> -#define CXL_FW_CANCEL BIT(0)
> +#define CXL_FW_CANCEL 0
>
> /**
> * struct cxl_fw_state - Firmware upload / activation state
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