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Date: Wed, 12 Jul 2023 16:10:09 +0530
From: Anup Patel <anup@...infault.org>
To: Heiko Stuebner <heiko@...ech.de>
Cc: palmer@...belt.com, paul.walmsley@...ive.com,
aou@...s.berkeley.edu, herbert@...dor.apana.org.au,
davem@...emloft.net, conor.dooley@...rochip.com,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-crypto@...r.kernel.org, christoph.muellner@...ll.eu,
ebiggers@...nel.org, Heiko Stuebner <heiko.stuebner@...ll.eu>
Subject: Re: [PATCH v4 04/12] RISC-V: add vector crypto extension detection
On Tue, Jul 11, 2023 at 9:09 PM Heiko Stuebner <heiko@...ech.de> wrote:
>
> From: Heiko Stuebner <heiko.stuebner@...ll.eu>
>
> Add detection for some extensions of the vector-crypto specification:
> - Zvkb: Vector Bit-manipulation used in Cryptography
> - Zvkg: Vector GCM/GMAC
> - Zvknha and Zvknhb: NIST Algorithm Suite
> - Zvkns: AES-128, AES-256 Single Round Suite
> - Zvksed: ShangMi Algorithm Suite
> - Zvksh: ShangMi Algorithm Suite
Any plan to allow user-space to detect these extensions via HWPROBE ?
Regards,
Anup
>
> As their use is very specific and will likely be limited to special places
> we expect current code to just pre-encode those instructions, so right now
> we don't introduce toolchain requirements.
>
> Signed-off-by: Heiko Stuebner <heiko.stuebner@...ll.eu>
> ---
> arch/riscv/include/asm/hwcap.h | 9 ++++++
> arch/riscv/kernel/cpu.c | 8 ++++++
> arch/riscv/kernel/cpufeature.c | 50 ++++++++++++++++++++++++++++++++++
> 3 files changed, 67 insertions(+)
>
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index b80ca6e77088..0f5172fa87b0 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -64,6 +64,15 @@
> #define RISCV_ISA_EXT_ZKSED 51
> #define RISCV_ISA_EXT_ZKSH 52
> #define RISCV_ISA_EXT_ZKT 53
> +#define RISCV_ISA_EXT_ZVBB 54
> +#define RISCV_ISA_EXT_ZVBC 55
> +#define RISCV_ISA_EXT_ZVKG 56
> +#define RISCV_ISA_EXT_ZVKNED 57
> +#define RISCV_ISA_EXT_ZVKNHA 58
> +#define RISCV_ISA_EXT_ZVKNHB 59
> +#define RISCV_ISA_EXT_ZVKSED 60
> +#define RISCV_ISA_EXT_ZVKSH 61
> +#define RISCV_ISA_EXT_ZVKT 62
>
> #define RISCV_ISA_EXT_MAX 64
> #define RISCV_ISA_EXT_NAME_LEN_MAX 32
> diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
> index 10524322a4c0..925241e25db2 100644
> --- a/arch/riscv/kernel/cpu.c
> +++ b/arch/riscv/kernel/cpu.c
> @@ -227,6 +227,14 @@ static struct riscv_isa_ext_data isa_ext_arr[] = {
> __RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED),
> __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH),
> __RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT),
> + __RISCV_ISA_EXT_DATA(zvbb, RISCV_ISA_EXT_ZVBB),
> + __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),
> + __RISCV_ISA_EXT_DATA(zvkg, RISCV_ISA_EXT_ZVKG),
> + __RISCV_ISA_EXT_DATA(zvkned, RISCV_ISA_EXT_ZVKNED),
> + __RISCV_ISA_EXT_DATA(zvknha, RISCV_ISA_EXT_ZVKNHA),
> + __RISCV_ISA_EXT_DATA(zvknhb, RISCV_ISA_EXT_ZVKNHB),
> + __RISCV_ISA_EXT_DATA(zvksed, RISCV_ISA_EXT_ZVKSED),
> + __RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH),
> __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
> __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
> __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 9a872a2007a5..13556fd16bf6 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -343,6 +343,56 @@ void __init riscv_fill_hwcap(void)
> SET_ISA_EXT_MAP("zksh", RISCV_ISA_EXT_ZKSH);
> SET_ISA_EXT_MAP("zkr", RISCV_ISA_EXT_ZKR);
> SET_ISA_EXT_MAP("zkt", RISCV_ISA_EXT_ZKT);
> + SET_ISA_EXT_MAP("zvbb", RISCV_ISA_EXT_ZVBB);
> + SET_ISA_EXT_MAP("zvbc", RISCV_ISA_EXT_ZVBC);
> + SET_ISA_EXT_MAP("zvkg", RISCV_ISA_EXT_ZVKG);
> + SET_ISA_EXT_MAP("zvkned", RISCV_ISA_EXT_ZVKNED);
> + SET_ISA_EXT_MAP("zvknha", RISCV_ISA_EXT_ZVKNHA);
> + SET_ISA_EXT_MAP("zvknhb", RISCV_ISA_EXT_ZVKNHB);
> + SET_ISA_EXT_MAP("zvksed", RISCV_ISA_EXT_ZVKSED);
> + SET_ISA_EXT_MAP("zvksh", RISCV_ISA_EXT_ZVKSH);
> + SET_ISA_EXT_MAP("zvkt", RISCV_ISA_EXT_ZVKT);
> +
> + /* NIST Algorithm Suite */
> + SET_ISA_EXT_MAP("zvkn", RISCV_ISA_EXT_ZVKNED);
> + SET_ISA_EXT_MAP("zvkn", RISCV_ISA_EXT_ZVKNHB);
> + SET_ISA_EXT_MAP("zvkn", RISCV_ISA_EXT_ZVBB);
> + SET_ISA_EXT_MAP("zvkn", RISCV_ISA_EXT_ZVKT);
> +
> + /* NIST Algorithm Suite with carryless multiply */
> + SET_ISA_EXT_MAP("zvknc", RISCV_ISA_EXT_ZVKNED);
> + SET_ISA_EXT_MAP("zvknc", RISCV_ISA_EXT_ZVKNHB);
> + SET_ISA_EXT_MAP("zvknc", RISCV_ISA_EXT_ZVBB);
> + SET_ISA_EXT_MAP("zvknc", RISCV_ISA_EXT_ZVKT);
> + SET_ISA_EXT_MAP("zvknc", RISCV_ISA_EXT_ZVBC);
> +
> + /* NIST Algorithm Suite with GCM */
> + SET_ISA_EXT_MAP("zvkng", RISCV_ISA_EXT_ZVKNED);
> + SET_ISA_EXT_MAP("zvkng", RISCV_ISA_EXT_ZVKNHB);
> + SET_ISA_EXT_MAP("zvkng", RISCV_ISA_EXT_ZVBB);
> + SET_ISA_EXT_MAP("zvkng", RISCV_ISA_EXT_ZVKT);
> + SET_ISA_EXT_MAP("zvkng", RISCV_ISA_EXT_ZVKG);
> +
> + /* ShangMi Algorithm Suite */
> + SET_ISA_EXT_MAP("zvks", RISCV_ISA_EXT_ZVKSED);
> + SET_ISA_EXT_MAP("zvks", RISCV_ISA_EXT_ZVKSH);
> + SET_ISA_EXT_MAP("zvks", RISCV_ISA_EXT_ZVBB);
> + SET_ISA_EXT_MAP("zvks", RISCV_ISA_EXT_ZVKT);
> +
> + /* ShangMi Algorithm Suite with carryless multiply */
> + SET_ISA_EXT_MAP("zvksc", RISCV_ISA_EXT_ZVKSED);
> + SET_ISA_EXT_MAP("zvksc", RISCV_ISA_EXT_ZVKSH);
> + SET_ISA_EXT_MAP("zvksc", RISCV_ISA_EXT_ZVBB);
> + SET_ISA_EXT_MAP("zvksc", RISCV_ISA_EXT_ZVKT);
> + SET_ISA_EXT_MAP("zvksc", RISCV_ISA_EXT_ZVBC);
> +
> + /* ShangMi Algorithm Suite with GCM */
> + SET_ISA_EXT_MAP("zvksg", RISCV_ISA_EXT_ZVKSED);
> + SET_ISA_EXT_MAP("zvksg", RISCV_ISA_EXT_ZVKSH);
> + SET_ISA_EXT_MAP("zvksg", RISCV_ISA_EXT_ZVBB);
> + SET_ISA_EXT_MAP("zvksg", RISCV_ISA_EXT_ZVKT);
> + SET_ISA_EXT_MAP("zvksg", RISCV_ISA_EXT_ZVKG);
> +
> }
> #undef SET_ISA_EXT_MAP
> }
> --
> 2.39.2
>
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