| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20230713090015.127541-4-william.qiu@starfivetech.com>
Date: Thu, 13 Jul 2023 17:00:15 +0800
From: William Qiu <william.qiu@...rfivetech.com>
To: <devicetree@...r.kernel.org>, <linux-spi@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-riscv@...ts.infradead.org>
CC: Mark Brown <broonie@...nel.org>, Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Emil Renner Berthing <kernel@...il.dk>,
Linus Walleij <linus.walleij@...aro.org>,
William Qiu <william.qiu@...rfivetech.com>
Subject: [PATCH v2 3/3] riscv: dts: starfive: Add spi node for JH7110 SoC
Add spi node for JH7110 SoC.
Signed-off-by: William Qiu <william.qiu@...rfivetech.com>
---
.../jh7110-starfive-visionfive-2.dtsi | 50 ++++++++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 98 +++++++++++++++++++
2 files changed, 148 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index fa0061eb33a7..ae3f39c33d3c 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -143,6 +143,18 @@ &i2c6 {
status = "okay";
};
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>;
+ status = "okay";
+
+ spi_dev0: flash@0 {
+ compatible = "rohm,dh2228fv";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ };
+};
+
&sysgpio {
i2c0_pins: i2c0-0 {
i2c-pins {
@@ -200,6 +212,44 @@ GPOEN_SYS_I2C6_DATA,
};
};
+ spi0_pins: spi0-0 {
+ mosi-pins {
+ pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,
+ GPOEN_ENABLE,
+ GPI_NONE)>;
+ bias-disable;
+ input-disable;
+ input-schmitt-disable;
+ };
+
+ miso-pins {
+ pinmux = <GPIOMUX(53, GPOUT_LOW,
+ GPOEN_DISABLE,
+ GPI_SYS_SPI0_RXD)>;
+ bias-pull-up;
+ input-enable;
+ input-schmitt-enable;
+ };
+
+ sck-pins {
+ pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_CLK,
+ GPOEN_ENABLE,
+ GPI_SYS_SPI0_CLK)>;
+ bias-disable;
+ input-disable;
+ input-schmitt-disable;
+ };
+
+ ss-pins {
+ pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_FSS,
+ GPOEN_ENABLE,
+ GPI_SYS_SPI0_FSS)>;
+ bias-disable;
+ input-disable;
+ input-schmitt-disable;
+ };
+ };
+
uart0_pins: uart0-0 {
tx-pins {
pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index ec2e70011a73..13da297c18fe 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -386,6 +386,48 @@ i2c2: i2c@...50000 {
status = "disabled";
};
+ spi0: spi@...60000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x0 0x10060000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_SPI0_APB>;
+ clock-names = "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_SPI0_APB>;
+ interrupts = <38>;
+ arm,primecell-periphid = <0x00041022>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi1: spi@...70000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x0 0x10070000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_SPI1_APB>;
+ clock-names = "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_SPI1_APB>;
+ interrupts = <39>;
+ arm,primecell-periphid = <0x00041022>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi2: spi@...80000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x0 0x10080000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_SPI2_APB>;
+ clock-names = "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_SPI2_APB>;
+ interrupts = <40>;
+ arm,primecell-periphid = <0x00041022>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
uart3: serial@...00000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x12000000 0x0 0x10000>;
@@ -473,6 +515,62 @@ i2c6: i2c@...60000 {
status = "disabled";
};
+ spi3: spi@...70000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x0 0x12070000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_SPI3_APB>;
+ clock-names = "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_SPI3_APB>;
+ interrupts = <52>;
+ arm,primecell-periphid = <0x00041022>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi4: spi@...80000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x0 0x12080000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_SPI4_APB>;
+ clock-names = "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_SPI4_APB>;
+ interrupts = <53>;
+ arm,primecell-periphid = <0x00041022>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi5: spi@...90000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x0 0x12090000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_SPI5_APB>;
+ clock-names = "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_SPI5_APB>;
+ interrupts = <54>;
+ arm,primecell-periphid = <0x00041022>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi6: spi@...a0000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x0 0x120A0000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_SPI6_APB>;
+ clock-names = "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_SPI6_APB>;
+ interrupts = <55>;
+ arm,primecell-periphid = <0x00041022>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
syscrg: clock-controller@...20000 {
compatible = "starfive,jh7110-syscrg";
reg = <0x0 0x13020000 0x0 0x10000>;
--
2.34.1
Powered by blists - more mailing lists