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Date:   Fri, 14 Jul 2023 14:59:28 +0900
From:   "Chanho Park" <chanho61.park@...sung.com>
To:     "'Krzysztof Kozlowski'" <krzysztof.kozlowski@...aro.org>,
        "'Jaewon Kim'" <jaewon02.kim@...sung.com>,
        "'Rob Herring'" <robh+dt@...nel.org>,
        "'Krzysztof Kozlowski'" <krzysztof.kozlowski+dt@...aro.org>,
        "'Conor Dooley'" <conor+dt@...nel.org>,
        "'Alim Akhtar'" <alim.akhtar@...sung.com>
Cc:     <devicetree@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-samsung-soc@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH] arm64: dts: exynos: add pwm node for exynosautov9-sadk

> > +			reg = <0x103f0000 0x100>;
> > +			samsung,pwm-outputs = <0>, <1>, <2>, <3>;
> > +			#pwm-cells = <3>;
> > +			clocks = <&xtcxo>;
> 
> This does not look like correct clock. Are you sure XTCXO goes to PWM?

Yes. XTXCO is the source clock of the pwm. Unlike any other exynos SoCs, the clock is directly derived from the external OSC.
Thus, it cannot be controllable such as gating.

Best Regards,
Chanho Park

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