linux-kernel - Re: [PATCH 09/10] arm64: dts: imx8ulp-evk: add 100MHz/200MHz pinctrl setting for eMMC

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Date:   Tue, 18 Jul 2023 11:32:27 +0800
From:   Shawn Guo <shawnguo@...nel.org>
To:     "Peng Fan (OSS)" <peng.fan@....nxp.com>
Cc:     robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
        s.hauer@...gutronix.de, kernel@...gutronix.de, festevam@...il.com,
        linux-imx@....com, devicetree@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        Haibo Chen <haibo.chen@....com>,
        Sherry Sun <sherry.sun@....com>, Peng Fan <peng.fan@....com>
Subject: Re: [PATCH 09/10] arm64: dts: imx8ulp-evk: add 100MHz/200MHz pinctrl
 setting for eMMC

On Sun, Jun 25, 2023 at 08:42:37PM +0800, Peng Fan (OSS) wrote:
> From: Haibo Chen <haibo.chen@....com>
> 
> Add 100MHz and 200MHz pinctrl setting for eMMC, and enable 8 bit bus mode
> to config the eMMC work at HS400ES mode.
> 
> Also update to use Standard Drive Strength for USDHC pad to get a better
> signal quality per Hardware team suggests.
> 
> Reviewed-by: Sherry Sun <sherry.sun@....com>
> Signed-off-by: Haibo Chen <haibo.chen@....com>
> Signed-off-by: Peng Fan <peng.fan@....com>
> ---
>  arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 26 ++++++++++---------
>  1 file changed, 14 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> index e459dc35e469..ab7af705bbca 100644
> --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> @@ -121,9 +121,11 @@ &lpuart5 {
>  };
>  
>  &usdhc0 {
> -	pinctrl-names = "default", "sleep";
> +	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
>  	pinctrl-0 = <&pinctrl_usdhc0>;
>  	pinctrl-1 = <&pinctrl_usdhc0>;
> +	pinctrl-2 = <&pinctrl_usdhc0>;
> +	pinctrl-3 = <&pinctrl_usdhc0>;

All three speed modes use the same pinctrl?

Shawn

>  	non-removable;
>  	bus-width = <8>;
>  	status = "okay";
> @@ -202,17 +204,17 @@ MX8ULP_PAD_PTF15__LPUART5_RX	0x3
>  
>  	pinctrl_usdhc0: usdhc0grp {
>  		fsl,pins = <
> -			MX8ULP_PAD_PTD1__SDHC0_CMD	0x43
> -			MX8ULP_PAD_PTD2__SDHC0_CLK	0x10042
> -			MX8ULP_PAD_PTD10__SDHC0_D0	0x43
> -			MX8ULP_PAD_PTD9__SDHC0_D1	0x43
> -			MX8ULP_PAD_PTD8__SDHC0_D2	0x43
> -			MX8ULP_PAD_PTD7__SDHC0_D3	0x43
> -			MX8ULP_PAD_PTD6__SDHC0_D4	0x43
> -			MX8ULP_PAD_PTD5__SDHC0_D5	0x43
> -			MX8ULP_PAD_PTD4__SDHC0_D6	0x43
> -			MX8ULP_PAD_PTD3__SDHC0_D7	0x43
> -			MX8ULP_PAD_PTD11__SDHC0_DQS	0x10042
> +			MX8ULP_PAD_PTD1__SDHC0_CMD	0x3
> +			MX8ULP_PAD_PTD2__SDHC0_CLK	0x10002
> +			MX8ULP_PAD_PTD10__SDHC0_D0	0x3
> +			MX8ULP_PAD_PTD9__SDHC0_D1	0x3
> +			MX8ULP_PAD_PTD8__SDHC0_D2	0x3
> +			MX8ULP_PAD_PTD7__SDHC0_D3	0x3
> +			MX8ULP_PAD_PTD6__SDHC0_D4	0x3
> +			MX8ULP_PAD_PTD5__SDHC0_D5	0x3
> +			MX8ULP_PAD_PTD4__SDHC0_D6	0x3
> +			MX8ULP_PAD_PTD3__SDHC0_D7	0x3
> +			MX8ULP_PAD_PTD11__SDHC0_DQS	0x10002
>  		>;
>  	};
>  };
> -- 
> 2.37.1
>