linux-kernel - RE: [PATCH 09/10] arm64: dts: imx8ulp-evk: add 100MHz/200MHz pinctrl setting for eMMC

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Message-ID: <DB7PR04MB4010E151615277AB6BD3E4CD9002A@DB7PR04MB4010.eurprd04.prod.outlook.com>
Date:   Mon, 24 Jul 2023 06:51:17 +0000
From:   Bough Chen <haibo.chen@....com>
To:     Shawn Guo <shawnguo@...nel.org>,
        "Peng Fan (OSS)" <peng.fan@....nxp.com>
CC:     "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "krzysztof.kozlowski+dt@...aro.org" 
        <krzysztof.kozlowski+dt@...aro.org>,
        "s.hauer@...gutronix.de" <s.hauer@...gutronix.de>,
        "kernel@...gutronix.de" <kernel@...gutronix.de>,
        "festevam@...il.com" <festevam@...il.com>,
        dl-linux-imx <linux-imx@....com>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Sherry Sun <sherry.sun@....com>, Peng Fan <peng.fan@....com>
Subject: RE: [PATCH 09/10] arm64: dts: imx8ulp-evk: add 100MHz/200MHz pinctrl
 setting for eMMC

> -----Original Message-----
> From: Shawn Guo <shawnguo@...nel.org>
> Sent: 2023年7月18日 11:32
> To: Peng Fan (OSS) <peng.fan@....nxp.com>
> Cc: robh+dt@...nel.org; krzysztof.kozlowski+dt@...aro.org;
> s.hauer@...gutronix.de; kernel@...gutronix.de; festevam@...il.com;
> dl-linux-imx <linux-imx@....com>; devicetree@...r.kernel.org;
> linux-arm-kernel@...ts.infradead.org; linux-kernel@...r.kernel.org; Bough
> Chen <haibo.chen@....com>; Sherry Sun <sherry.sun@....com>; Peng Fan
> <peng.fan@....com>
> Subject: Re: [PATCH 09/10] arm64: dts: imx8ulp-evk: add 100MHz/200MHz
> pinctrl setting for eMMC
> 
> On Sun, Jun 25, 2023 at 08:42:37PM +0800, Peng Fan (OSS) wrote:
> > From: Haibo Chen <haibo.chen@....com>
> >
> > Add 100MHz and 200MHz pinctrl setting for eMMC, and enable 8 bit bus
> > mode to config the eMMC work at HS400ES mode.
> >
> > Also update to use Standard Drive Strength for USDHC pad to get a
> > better signal quality per Hardware team suggests.
> >
> > Reviewed-by: Sherry Sun <sherry.sun@....com>
> > Signed-off-by: Haibo Chen <haibo.chen@....com>
> > Signed-off-by: Peng Fan <peng.fan@....com>
> > ---
> >  arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 26
> > ++++++++++---------
> >  1 file changed, 14 insertions(+), 12 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> > b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> > index e459dc35e469..ab7af705bbca 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> > @@ -121,9 +121,11 @@ &lpuart5 {
> >  };
> >
> >  &usdhc0 {
> > -	pinctrl-names = "default", "sleep";
> > +	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
> >  	pinctrl-0 = <&pinctrl_usdhc0>;
> >  	pinctrl-1 = <&pinctrl_usdhc0>;
> > +	pinctrl-2 = <&pinctrl_usdhc0>;
> > +	pinctrl-3 = <&pinctrl_usdhc0>;
> 
> All three speed modes use the same pinctrl?

Yes, the IOMUX on imx8ulp do not support config different drive strength. So here use the same pinctrl.

Best Regards
Haibo Chen
> 
> Shawn
> 
> >  	non-removable;
> >  	bus-width = <8>;
> >  	status = "okay";
> > @@ -202,17 +204,17 @@ MX8ULP_PAD_PTF15__LPUART5_RX	0x3
> >
> >  	pinctrl_usdhc0: usdhc0grp {
> >  		fsl,pins = <
> > -			MX8ULP_PAD_PTD1__SDHC0_CMD	0x43
> > -			MX8ULP_PAD_PTD2__SDHC0_CLK	0x10042
> > -			MX8ULP_PAD_PTD10__SDHC0_D0	0x43
> > -			MX8ULP_PAD_PTD9__SDHC0_D1	0x43
> > -			MX8ULP_PAD_PTD8__SDHC0_D2	0x43
> > -			MX8ULP_PAD_PTD7__SDHC0_D3	0x43
> > -			MX8ULP_PAD_PTD6__SDHC0_D4	0x43
> > -			MX8ULP_PAD_PTD5__SDHC0_D5	0x43
> > -			MX8ULP_PAD_PTD4__SDHC0_D6	0x43
> > -			MX8ULP_PAD_PTD3__SDHC0_D7	0x43
> > -			MX8ULP_PAD_PTD11__SDHC0_DQS	0x10042
> > +			MX8ULP_PAD_PTD1__SDHC0_CMD	0x3
> > +			MX8ULP_PAD_PTD2__SDHC0_CLK	0x10002
> > +			MX8ULP_PAD_PTD10__SDHC0_D0	0x3
> > +			MX8ULP_PAD_PTD9__SDHC0_D1	0x3
> > +			MX8ULP_PAD_PTD8__SDHC0_D2	0x3
> > +			MX8ULP_PAD_PTD7__SDHC0_D3	0x3
> > +			MX8ULP_PAD_PTD6__SDHC0_D4	0x3
> > +			MX8ULP_PAD_PTD5__SDHC0_D5	0x3
> > +			MX8ULP_PAD_PTD4__SDHC0_D6	0x3
> > +			MX8ULP_PAD_PTD3__SDHC0_D7	0x3
> > +			MX8ULP_PAD_PTD11__SDHC0_DQS	0x10002
> >  		>;
> >  	};
> >  };
> > --
> > 2.37.1
> >