linux-kernel - Re: [PATCH v8 0/9] Add STG/ISP/VOUT clock and reset drivers for StarFive JH7110

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Message-ID: <20230721-copier-mystify-311b6367f5f8@spud>
Date:   Fri, 21 Jul 2023 10:32:41 +0100
From:   Conor Dooley <conor@...nel.org>
To:     Xingyu Wu <xingyu.wu@...rfivetech.com>
Cc:     linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Emil Renner Berthing <emil.renner.berthing@...onical.com>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Hal Feng <hal.feng@...rfivetech.com>,
        linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org
Subject: Re: [PATCH v8 0/9] Add STG/ISP/VOUT clock and reset drivers for
 StarFive JH7110

On Fri, Jul 21, 2023 at 02:41:56PM +0800, Xingyu Wu wrote:
> On 2023/7/21 0:32, Conor Dooley wrote:
> > On Thu, Jul 13, 2023 at 07:38:53PM +0800, Xingyu Wu wrote:
> >> This patch serises are base on the basic JH7110 SYSCRG/AONCRG
> >> drivers and add new partial clock drivers and reset supports
> >> about System-Top-Group(STG), Image-Signal-Process(ISP)
> >> and Video-Output(VOUT) for the StarFive JH7110 RISC-V SoC. These
> >> clocks and resets could be used by DMA, VIN and Display modules.
> >> 
> >> Patches 1 and 2 are about the System-Top-Group clock and reset
> >> generator(STGCRG) part. The first patch adds docunmentation to
> >> describe STG bindings, and the second patch adds clock driver to
> >> support STG clocks and resets as auxiliary device for JH7110.
> >> 
> >> Patches 3 and 4 are about the Image-Signal-Process clock and reset
> >> gennerator(ISPCRG) part. The first patch adds docunmentation to
> >> describe ISP bindings, and the second patch adds clock driver to
> >> support ISP clocks and resets as auxiliary device for JH7110.
> >> And ISP clocks should power on and enable the SYSCRG clocks first
> >> before registering.
> >> 
> >> Patches 5 and 6 are about the Video-Output clock and reset
> >> generator(VOUTCRG) part. The first patch adds docunmentation to
> >> describe VOUT bindings, and the second patch adds clock driver to
> >> support VOUT clocks and resets as auxiliary device for JH7110.
> >> And VOUT clocks also should power on and enable the SYSCRG clocks
> >> first before registering.
> >> 
> >> Patch 7 adds struct members to support STG/ISP/VOUT resets.
> 
> BTW, I found this patch is not in the linux-next or clk-next.
> These STG/ISP/VOUT CRG drivers are 'incomplete' without this resets patch.
> I don't know what your plans about this patch and I'm just curious on it.

Oh. I mistakenly thought that this was a standalone reset controller
patch that Philipp could take, but now I see it depends on the 
dt-binding headers added by this series.
Maybe you could resend it by itself, and Stephen could pick it into
clk-next?

Sorry about that,
Conor.

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