linux-kernel - Re: [PATCH v2 00/11] Unify TDCALL/SEAMCALL and TDVMCALL assembly

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Message-ID: <a23ce8fd289141cea3a1b4f3dace221dca847238.camel@intel.com>
Date:   Fri, 21 Jul 2023 00:18:23 +0000
From:   "Huang, Kai" <kai.huang@...el.com>
To:     "peterz@...radead.org" <peterz@...radead.org>
CC:     "Hansen, Dave" <dave.hansen@...el.com>,
        "Christopherson,, Sean" <seanjc@...gle.com>,
        "bp@...en8.de" <bp@...en8.de>, "x86@...nel.org" <x86@...nel.org>,
        "hpa@...or.com" <hpa@...or.com>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "kirill.shutemov@...ux.intel.com" <kirill.shutemov@...ux.intel.com>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "pbonzini@...hat.com" <pbonzini@...hat.com>,
        "Yamahata, Isaku" <isaku.yamahata@...el.com>,
        "sathyanarayanan.kuppuswamy@...ux.intel.com" 
        <sathyanarayanan.kuppuswamy@...ux.intel.com>,
        "n.borisov.lkml@...il.com" <n.borisov.lkml@...il.com>
Subject: Re: [PATCH v2 00/11] Unify TDCALL/SEAMCALL and TDVMCALL assembly

On Thu, 2023-07-20 at 15:16 +0200, Peter Zijlstra wrote:
> On Fri, Jul 21, 2023 at 12:28:03AM +1200, Kai Huang wrote:
> 
> > Kai Huang (11):
> >   x86/tdx: Zero out the missing RSI in TDX_HYPERCALL macro
> >   x86/tdx: Skip saving output regs when SEAMCALL fails with
> >     VMFailInvalid
> >   x86/tdx: Make macros of TDCALLs consistent with the spec
> >   x86/tdx: Rename __tdx_module_call() to __tdcall()
> >   x86/tdx: Pass TDCALL/SEAMCALL input/output registers via a structure
> >   x86/tdx: Extend TDX_MODULE_CALL to support more TDCALL/SEAMCALL leafs
> >   x86/tdx: Make TDX_HYPERCALL asm similar to TDX_MODULE_CALL
> >   x86/tdx: Reimplement __tdx_hypercall() using TDX_MODULE_CALL asm
> >   x86/tdx: Remove 'struct tdx_hypercall_args'
> >   x86/virt/tdx: Wire up basic SEAMCALL functions
> >   x86/virt/tdx: Allow SEAMCALL to handle #UD and #GP
> 
> These look ok to me, thanks!

Thanks!

> 
> This does not yet re-order the args structure to conform to the hardware
> index order as per kvm's requirement, right? That will be part of the
> KVM series?

Unfortunately I don't think it's feasible.  Sean pointed out that
kvm_vcpu_arch::regs[] do follow the "register index" hardware layout in x86 (for
which I missed sorry), so we cannot re-order KVM part.  

And unfortunately RBP (5) is in middle of those registers:

	0 = RAX
	1 = RCX
	2 = RDX
	3 = RBX
	4 = RSP
	5 = RBP
	6 = RSI
	7 = RDI
	8–15 represent R8–R15, respectively...

Thus unless we add RBP to 'struct tdx_module_args', it's impossible to re-order
the structure to match KVM's layout.