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Message-ID: <20230724210228.GA3749554@hirez.programming.kicks-ass.net>
Date: Mon, 24 Jul 2023 23:02:28 +0200
From: Peter Zijlstra <peterz@...radead.org>
To: Thomas Gleixner <tglx@...utronix.de>
Cc: LKML <linux-kernel@...r.kernel.org>, x86@...nel.org,
Tom Lendacky <thomas.lendacky@....com>,
Andrew Cooper <andrew.cooper3@...rix.com>,
Arjan van de Ven <arjan@...ux.intel.com>,
"James E.J. Bottomley" <jejb@...ux.ibm.com>,
Dick Kennedy <dick.kennedy@...adcom.com>,
James Smart <james.smart@...adcom.com>,
"Martin K. Petersen" <martin.petersen@...cle.com>,
linux-scsi@...r.kernel.org, linux-hwmon@...r.kernel.org,
Jean Delvare <jdelvare@...e.com>,
Huang Rui <ray.huang@....com>,
Guenter Roeck <linux@...ck-us.net>,
Steve Wahl <steve.wahl@....com>,
Mike Travis <mike.travis@....com>,
Dimitri Sivanich <dimitri.sivanich@....com>,
Russ Anderson <russ.anderson@....com>
Subject: Re: [patch 17/29] x86/cpu: Provide a sane leaf 0xb/0x1f parser
On Mon, Jul 24, 2023 at 10:49:42PM +0200, Peter Zijlstra wrote:
> On Mon, Jul 24, 2023 at 07:44:17PM +0200, Thomas Gleixner wrote:
>
> > +static inline bool topo_subleaf(struct topo_scan *tscan, u32 leaf, u32 subleaf)
> > +{
> > + unsigned int dom, maxtype = leaf == 0xb ? CORE_TYPE + 1 : MAX_TYPE;
> > + struct {
> > + // eax
> > + u32 x2apic_shift : 5, // Number of bits to shift APIC ID right
> > + // for the topology ID at the next level
> > + __rsvd0 : 27; // Reserved
> > + // ebx
> > + u32 num_processors : 16, // Number of processors at current level
> > + __rsvd1 : 16; // Reserved
> > + // ecx
> > + u32 level : 8, // Current topology level. Same as sub leaf number
> > + type : 8, // Level type. If 0, invalid
> > + __rsvd2 : 16; // Reserved
> > + // edx
> > + u32 x2apic_id : 32; // X2APIC ID of the current logical processor
>
> That comment seems inconsistent, either have then all aligned or move
> all register names left.
AMD code seems to have the reg names left aligned -- perhaps do the same
here.
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