linux-kernel - Re: [PATCH v1] arm64: dts: qcom: sc7280: Add PCIe0 node

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Message-ID: <a2024453-e749-b659-52a0-83ded8bb5c38@linaro.org>
Date:   Fri, 28 Jul 2023 17:57:44 +0200
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Krishna Chaitanya Chundru <quic_krichai@...cinc.com>,
        manivannan.sadhasivam@...aro.org
Cc:     helgaas@...nel.org, linux-pci@...r.kernel.org,
        linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
        quic_vbadigan@...cinc.com, quic_nitegupt@...cinc.com,
        quic_skananth@...cinc.com, quic_ramkri@...cinc.com,
        quic_parass@...cinc.com,
        "reviewer:ARM/QUALCOMM CHROMEBOOK SUPPORT" 
        <cros-qcom-dts-watchers@...omium.org>,
        Andy Gross <agross@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konrad.dybcio@...aro.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
Subject: Re: [PATCH v1] arm64: dts: qcom: sc7280: Add PCIe0 node

On 28/07/2023 17:10, Krishna Chaitanya Chundru wrote:
> 
> On 7/28/2023 5:33 PM, Krzysztof Kozlowski wrote:
>> On 28/07/2023 12:39, Krishna chaitanya chundru wrote:
>>> Add PCIe dtsi node for PCIe0 controller on sc7280 platform.
>>>
>>> Signed-off-by: Krishna chaitanya chundru <quic_krichai@...cinc.com>
>> Thank you for your patch. There is something to discuss/improve.
>>
>>
>>> +		pcie0_phy: phy@...6000 {
>>> +			compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
>>> +			reg = <0 0x01c06000 0 0x1c0>;
>>> +			#address-cells = <2>;
>>> +			#size-cells = <2>;
>>> +			ranges;
>>> +			clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
>>> +				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
>>> +				 <&gcc GCC_PCIE_CLKREF_EN>,
>>> +				 <&gcc GCC_PCIE0_PHY_RCHNG_CLK>;
>>> +			clock-names = "aux", "cfg_ahb", "ref", "refgen";
>>> +
>>> +			resets = <&gcc GCC_PCIE_0_PHY_BCR>;
>>> +			reset-names = "phy";
>>> +
>>> +			assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>;
>>> +			assigned-clock-rates = <100000000>;
>>> +
>>> +			status = "disabled";
>>> +
>>> +			pcie0_lane: phy@...e6200 {
>> Isn't this old-style of bindings? Wasn't there a change? On what tree
>> did you base it?

The work was here:
https://lore.kernel.org/all/20230324022514.1800382-5-dmitry.baryshkov@linaro.org/

But I don't remember the status.

> Let me rebase and send it again.

This anyway looks like wrong compatible. You used sm8250.


Best regards,
Krzysztof