linux-kernel - Re: [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller

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Message-ID: <be748338-987b-d474-d040-82af7cfb5f01@linaro.org>
Date:   Fri, 28 Jul 2023 08:58:25 +0200
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Eric Lin <eric.lin@...ive.com>
Cc:     robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
        conor+dt@...nel.org, devicetree@...r.kernel.org,
        linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
        zong.li@...ive.com, greentime.hu@...ive.com,
        vincent.chen@...ive.com
Subject: Re: [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2
 cache controller

On 28/07/2023 08:01, Eric Lin wrote:
> Hi Krzysztof,
> 
> On Fri, Jul 21, 2023 at 4:35 PM Krzysztof Kozlowski
> <krzysztof.kozlowski@...aro.org> wrote:
>>
>> On 20/07/2023 15:51, Eric Lin wrote:
>>> This add YAML DT binding documentation for SiFive Private L2
>>> cache controller
>>>
>>> Signed-off-by: Eric Lin <eric.lin@...ive.com>
>>> Reviewed-by: Zong Li <zong.li@...ive.com>
>>> Reviewed-by: Nick Hu <nick.hu@...ive.com>
>>
>>
>> ...
>>
>>> +properties:
>>> +  compatible:
>>> +    items:
>>> +      - const: sifive,pl2cache1
>>
>> I still have doubts that it is not used in any SoC. This is what you
>> said last time: "is not part of any SoC."
>> If not part of any SoC, then where is it? Why are you adding it to the
>> kernel?
>>
> 
> Sorry for the late reply. I didn't describe it clearly last time.
> Currently, we have two hardware versions of pl2cache: pl2cache0 and pl2cache1.
> The pl2cache0 is used in unmatched board SoC. The pl2cache1 is
> utilized in our internal FPGA platform for evaluation; it's our core
> IP.

And why do you add bindings for some internal FPGA IP block which does
not interface with any SW?

Best regards,
Krzysztof