lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <de822fa6-16ca-381c-2cdf-7e983f29945b@pengutronix.de>
Date:   Mon, 31 Jul 2023 09:00:29 +0200
From:   Johannes Zink <j.zink@...gutronix.de>
To:     Richard Cochran <richardcochran@...il.com>
Cc:     Giuseppe Cavallaro <peppe.cavallaro@...com>,
        Alexandre Torgue <alexandre.torgue@...s.st.com>,
        Jose Abreu <joabreu@...opsys.com>,
        "David S. Miller" <davem@...emloft.net>,
        Eric Dumazet <edumazet@...gle.com>,
        Jakub Kicinski <kuba@...nel.org>,
        Paolo Abeni <pabeni@...hat.com>,
        Maxime Coquelin <mcoquelin.stm32@...il.com>,
        Russell King <linux@...linux.org.uk>,
        patchwork-jzi@...gutronix.de, netdev@...r.kernel.org,
        linux-stm32@...md-mailman.stormreply.com,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        kernel@...gutronix.de, kernel test robot <lkp@...el.com>
Subject: Re: [PATCH v2] net: stmmac: correct MAC propagation delay

Hi Richard,

On 7/27/23 15:36, Richard Cochran wrote:
> On Thu, Jul 27, 2023 at 09:20:10AM +0200, Johannes Zink wrote:
>> Hi Richard,
>>
>> On 7/26/23 22:57, Richard Cochran wrote:
>>> On Mon, Jul 24, 2023 at 12:01:31PM +0200, Johannes Zink wrote:
>>>
>>> Earlier versions of the IP core return zero from these...
>>>
>>>> +#define	PTP_TS_INGR_LAT	0x68	/* MAC internal Ingress Latency */
>>>> +#define	PTP_TS_EGR_LAT	0x6c	/* MAC internal Egress Latency */
>>>
>>
>> good catch. Gonna send a v3 with a check to and set the values for dwmac v5 only.
> 
> AFAICT there is no feature bit that indicates the presence or absence
> of these two registers.
> 
> Are you sure that *all* v5 IP cores have these?
> 
> I am not sure.

I cannot tell for sure either, since I have datasheets for the i.MX8MP only. 
Maybe Kurt has some insights here, as he has additional hardware available for 
testing?

Nevertheless, I am going to add a guard to only use the correction codepath on 
i.MX8MP in v3 for the time being, we can add other hardware later trivially if 
they support doing this.

Best regards
Johannes

> 
> Thanks,
> Richard
> 
> 

-- 
Pengutronix e.K.                | Johannes Zink                  |
Steuerwalder Str. 21            | https://www.pengutronix.de/    |
31137 Hildesheim, Germany       | Phone: +49-5121-206917-0       |
Amtsgericht Hildesheim, HRA 2686| Fax:   +49-5121-206917-5555    |

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ