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Message-ID: <6581496b-57e8-d5bf-ae3e-fb466ed5dff9@linux.alibaba.com>
Date: Mon, 31 Jul 2023 20:31:33 +0800
From: Jing Zhang <renyu.zj@...ux.alibaba.com>
To: John Garry <john.g.garry@...cle.com>,
Ian Rogers <irogers@...gle.com>
Cc: Will Deacon <will@...nel.org>, Mark Rutland <mark.rutland@....com>,
Robin Murphy <robin.murphy@....com>,
Ilkka Koskinen <ilkka@...amperecomputing.com>,
Namhyung Kim <namhyung@...nel.org>,
Arnaldo Carvalho de Melo <acme@...nel.org>,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-perf-users@...r.kernel.org, linux-doc@...r.kernel.org,
Zhuo Song <zhuo.song@...ux.alibaba.com>,
Shuai Xue <xueshuai@...ux.alibaba.com>
Subject: Re: [PATCH v5 4/5] perf jevents: Add support for Arm CMN PMU aliasing
在 2023/7/28 下午4:17, John Garry 写道:
> On 28/07/2023 07:17, Jing Zhang wrote:
>> Currently just add aliases for part of Arm CMN PMU events which are
>> general and compatible for any SoC and CMN-ANY.
>>
>> "Compat" value "434*;436*;43c*;43a*" means it is compatible with all
>
> As mentioned in patch 1/5, a comma-separated list seems a better delimiter to me
>
>> CMN600/CMN650/CMN700/Ci700.
>
> It would be good if you could provide a link to where you got these events. I think that it is the publicly available CMN TRM document.
>
Ok, will do.
Thanks,
Jing
>>
>> Signed-off-by: Jing Zhang<renyu.zj@...ux.alibaba.com>
>
> Apart from comments, above:
>
> Reviewed-by: John Garry <john.g.garry@...cle.com>
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