linux-kernel - Re: [PATCH] LoongArch: Fixup cmpxchg sematic for memory barrier

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Message-ID: <CAHirt9ggujWPw7KV7qSGjk=-nX16U+u1MwNGSLEkoogcJjOHFA@mail.gmail.com>
Date:   Tue, 1 Aug 2023 17:30:33 +0800
From:   WANG Rui <wangrui@...ngson.cn>
To:     Will Deacon <will@...nel.org>
Cc:     guoren@...nel.org, chenhuacai@...nel.or, kernel@...0n.name,
        arnd@...db.de, andi.shyti@...ux.intel.com, andrzej.hajda@...el.com,
        peterz@...radead.org, boqun.feng@...il.com, mark.rutland@....com,
        loongarch@...ts.linux.dev, linux-kernel@...r.kernel.org,
        Guo Ren <guoren@...ux.alibaba.com>
Subject: Re: [PATCH] LoongArch: Fixup cmpxchg sematic for memory barrier

Hello,

On Tue, Aug 1, 2023 at 4:32 PM Will Deacon <will@...nel.org> wrote:
>
> Hmm, somehow this one passed me by, but I think that puts you in the naughty
> corner with Itanium. It probably also means your READ_ONCE() is broken,
> unless the compiler emits barriers for volatile reads (like ia64)?

Hmm, I agree with your perspective. Allowing out-of-order loads for
the same address in the memory model provides certain performance
benefits, but it also poses challenges to software. Fortunately,
hardware supports software to disable this feature when needed.

Regards,
-- 
WANG Rui