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Message-ID: <20230805064820.30305-1-zhifeng.tang@unisoc.com>
Date: Sat, 5 Aug 2023 14:48:20 +0800
From: Zhifeng Tang <zhifeng.tang@...soc.com>
To: Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Orson Zhai <orsonzhai@...il.com>,
Baolin Wang <baolin.wang@...ux.alibaba.com>,
Chunyan Zhang <zhang.lyra@...il.com>,
Zhifeng Tang <zhifeng.tang@...soc.com>,
Cixi Geng <cixi.geng1@...soc.com>
CC: <linux-clk@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
Zhifeng Tang <zhifeng.tang23@...il.com>,
Wenming Wu <wenming.wu@...soc.com>
Subject: [PATCH] clk: sprd: Fix thm_parents incorrect configuration
The thm*_clk have two clock sources 32k and 250k,excluding 32m.
Signed-off-by: Zhifeng Tang <zhifeng.tang@...soc.com>
---
drivers/clk/sprd/ums512-clk.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sprd/ums512-clk.c b/drivers/clk/sprd/ums512-clk.c
index fc25bdd85e4e..f43bb10bd5ae 100644
--- a/drivers/clk/sprd/ums512-clk.c
+++ b/drivers/clk/sprd/ums512-clk.c
@@ -800,7 +800,7 @@ static SPRD_MUX_CLK_DATA(uart1_clk, "uart1-clk", uart_parents,
0x250, 0, 3, UMS512_MUX_FLAG);
static const struct clk_parent_data thm_parents[] = {
- { .fw_name = "ext-32m" },
+ { .fw_name = "ext-32k" },
{ .hw = &clk_250k.hw },
};
static SPRD_MUX_CLK_DATA(thm0_clk, "thm0-clk", thm_parents,
--
2.17.1
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