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Message-ID: <6535a243-b69c-8571-2d2c-c686f25a9dc5@arm.com>
Date: Mon, 7 Aug 2023 12:15:00 +0100
From: Suzuki K Poulose <suzuki.poulose@....com>
To: Tao Zhang <quic_taozha@...cinc.com>,
Mathieu Poirier <mathieu.poirier@...aro.org>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Konrad Dybcio <konradybcio@...il.com>,
Mike Leach <mike.leach@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>
Cc: Jinlong Mao <quic_jinlmao@...cinc.com>,
Leo Yan <leo.yan@...aro.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
coresight@...ts.linaro.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
Tingwei Zhang <quic_tingweiz@...cinc.com>,
Yuanfang Zhang <quic_yuanfang@...cinc.com>,
Trilok Soni <quic_tsoni@...cinc.com>,
Hao Zhang <quic_hazha@...cinc.com>,
linux-arm-msm@...r.kernel.org, andersson@...nel.org
Subject: Re: [PATCH v7 10/13] coresight-tpdm: Add nodes to configure pattern
match output
On 25/07/2023 08:15, Tao Zhang wrote:
> Add nodes to configure trigger pattern and trigger pattern mask.
> Each DSB subunit TPDM has maximum of n(n<7) XPR registers to
> configure trigger pattern match output. Eight 32 bit registers
> providing DSB interface trigger output pattern match comparison.
> And each DSB subunit TPDM has maximum of m(m<7) XPMR registers to
> configure trigger pattern mask match output. Eight 32 bit
> registers providing DSB interface trigger output pattern match
> mask.
>
> Signed-off-by: Tao Zhang <quic_taozha@...cinc.com>
> ---
> .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 34 +++++-
> drivers/hwtracing/coresight/coresight-tpdm.c | 118 +++++++++++++++++++++
> drivers/hwtracing/coresight/coresight-tpdm.h | 10 ++
> 3 files changed, 161 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
> index a4550c5..66f9582 100644
> --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
> @@ -98,4 +98,36 @@ Description:
> should be written first to configure the index number of the edge
> detection which needs to be masked.
>
> - Accepts only one of the 2 values - 0 or 1.
> \ No newline at end of file
> + Accepts only one of the 2 values - 0 or 1.
> +
> +What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt_idx
> +Date: March 2023
> +KernelVersion 6.5
> +Contact: Jinlong Mao (QUIC) <quic_jinlmao@...cinc.com>, Tao Zhang (QUIC) <quic_taozha@...cinc.com>
> +Description:
> + Read/Write the index number of the trigger pattern value of DSB
> + tpdm. Since there are at most 8 XPR and XPMR registers for the
> + trigger parttern, this value ranges from 0 to 7.
> +
> +What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt_val
> +Date: March 2023
> +KernelVersion 6.5
> +Contact: Jinlong Mao (QUIC) <quic_jinlmao@...cinc.com>, Tao Zhang (QUIC) <quic_taozha@...cinc.com>
> +Description:
> + Read a set of the trigger pattern values of the DSB TPDM.
> + Write a data to configure the trigger pattern corresponding to
> + the index number. Before writing data to this sysfs file,
> + "dsb_trig_patt_idx" should be written first to configure the
> + index number of the trigger pattern which needs to be configured.
> +
> +What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt_mask
> +Date: March 2023
> +KernelVersion 6.5
> +Contact: Jinlong Mao (QUIC) <quic_jinlmao@...cinc.com>, Tao Zhang (QUIC) <quic_taozha@...cinc.com>
> +Description:
> + Read a set of the trigger pattern mask of the DSB TPDM.
> + Write a data to configure the trigger pattern mask corresponding
> + to the index number. Before writing data to this sysfs file,
> + "dsb_trig_patt_idx" should be written first to configure the
> + index number of the trigger pattern mask which needs to be
> + configured.
> \ No newline at end of file
> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c
> index 98fd6ab..1c32d27 100644
> --- a/drivers/hwtracing/coresight/coresight-tpdm.c
> +++ b/drivers/hwtracing/coresight/coresight-tpdm.c
> @@ -80,6 +80,13 @@ static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata)
> writel_relaxed(drvdata->dsb->edge_ctrl_mask[i],
> drvdata->base + TPDM_DSB_EDCMR(i));
>
> + for (i = 0; i < TPDM_DSB_MAX_PATT; i++) {
> + writel_relaxed(drvdata->dsb->trig_patt[i],
> + drvdata->base + TPDM_DSB_XPR(i));
> + writel_relaxed(drvdata->dsb->trig_patt_mask[i],
> + drvdata->base + TPDM_DSB_XPMR(i));
> + }
> +
> val = readl_relaxed(drvdata->base + TPDM_DSB_TIER);
> /* Set trigger timestamp */
> if (drvdata->dsb->trig_ts)
> @@ -455,6 +462,114 @@ static ssize_t dsb_edge_ctrl_mask_store(struct device *dev,
> }
> static DEVICE_ATTR_RW(dsb_edge_ctrl_mask);
>
> +static ssize_t dsb_trig_patt_idx_show(struct device *dev,
> + struct device_attribute *attr,
> + char *buf)
> +{
> + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
> +
> + return sysfs_emit(buf, "%u\n",
> + (unsigned int)drvdata->dsb->trig_patt_idx);
> +}
> +
> +static ssize_t dsb_trig_patt_idx_store(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf,
> + size_t size)
> +{
> + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + unsigned long index;
> +
> + if (kstrtoul(buf, 0, &index))
> + return -EINVAL;
> + if (index >= TPDM_DSB_MAX_PATT)
> + return -EPERM;
> +
> + spin_lock(&drvdata->spinlock);
> + drvdata->dsb->trig_patt_idx = index;
> + spin_unlock(&drvdata->spinlock);
> + return size;
> +}
> +static DEVICE_ATTR_RW(dsb_trig_patt_idx);
> +
> +static ssize_t dsb_trig_patt_val_show(struct device *dev,
> + struct device_attribute *attr,
> + char *buf)
> +{
> + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + ssize_t size = 0;
> + unsigned long bytes;
> + int i = 0;
> +
> + spin_lock(&drvdata->spinlock);
> + for (i = 0; i < TPDM_DSB_MAX_PATT; i++) {
> + bytes = sysfs_emit_at(buf, size,
> + "Value: 0x%x\n", drvdata->dsb->trig_patt[i]);
> + if (bytes <= 0)
> + break;
> + size += bytes;
> + }
> + spin_unlock(&drvdata->spinlock);
> + return size;
> +}
> +
> +static ssize_t dsb_trig_patt_val_store(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf,
> + size_t size)
> +{
> + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + unsigned long val;
> +
> + if (kstrtoul(buf, 0, &val))
> + return -EINVAL;
> +
> + spin_lock(&drvdata->spinlock);
> + drvdata->dsb->trig_patt[drvdata->dsb->trig_patt_idx] = val;
> + spin_unlock(&drvdata->spinlock);
> + return size;
> +}
> +static DEVICE_ATTR_RW(dsb_trig_patt_val);
> +
> +static ssize_t dsb_trig_patt_mask_show(struct device *dev,
> + struct device_attribute *attr,
> + char *buf)
> +{
> + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + ssize_t size = 0;
> + unsigned long bytes;
> + int i = 0;
> +
> + spin_lock(&drvdata->spinlock);
> + for (i = 0; i < TPDM_DSB_MAX_PATT; i++) {
> + bytes = sysfs_emit_at(buf, size,
> + "Value: 0x%x\n", drvdata->dsb->trig_patt_mask[i]);
As mentioned above, please stick to single value. In this case, we could
simply expose :
dsb_trig_patt_mask0..7 as RW and directly let the user set/get the
values and get rid of the idx.
You may be able to use an device_ext_attribute to store the index and
use a single function to support all registers.
Suzuki
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