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Message-ID: <ff316b1f-d4b5-6a02-b4e3-d73e122197ff@quicinc.com>
Date: Mon, 7 Aug 2023 17:26:16 +0530
From: Komal Bajaj <quic_kbajaj@...cinc.com>
To: Mukesh Ojha <quic_mojha@...cinc.com>, <agross@...nel.org>,
<andersson@...nel.org>, <konrad.dybcio@...aro.org>,
<robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
<conor+dt@...nel.org>, <srinivas.kandagatla@...aro.org>
CC: <linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v6 6/6] soc: qcom: llcc: Add QDU1000 and QRU1000 LLCC
support
On 8/3/2023 6:39 PM, Mukesh Ojha wrote:
>
>
> On 8/2/2023 2:44 PM, Komal Bajaj wrote:
>> Add LLCC configuration data for QDU1000 and QRU1000 SoCs.
>>
>> Signed-off-by: Komal Bajaj <quic_kbajaj@...cinc.com>
>> ---
>> drivers/soc/qcom/llcc-qcom.c | 67 ++++++++++++++++++++++++++++++++++++
>> 1 file changed, 67 insertions(+)
>>
>> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
>> index 315f7a1b90aa..8e1b2399700d 100644
>> --- a/drivers/soc/qcom/llcc-qcom.c
>> +++ b/drivers/soc/qcom/llcc-qcom.c
>> @@ -366,6 +366,36 @@ static const struct llcc_slice_config
>> sm8550_data[] = {
>> {LLCC_VIDVSP, 28, 256, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0,
>> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
>> };
>>
>> +static const struct llcc_slice_config qdu1000_data_2ch[] = {
>> + { LLCC_MDMHPGRW, 7, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
>> + { LLCC_MODHW, 9, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
>> + { LLCC_MDMPNG, 21, 256, 0, 1, 0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 },
>> + { LLCC_ECC, 26, 512, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 },
>> + { LLCC_MODPE, 29, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
>> + { LLCC_APTCM, 30, 256, 3, 1, 0x0, 0xc, 1, 0, 0, 1, 0, 0, 0 },
>> + { LLCC_WRCACHE, 31, 128, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 },
>> +};
>> +
>> +static const struct llcc_slice_config qdu1000_data_4ch[] = {
>> + { LLCC_MDMHPGRW, 7, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
>> + { LLCC_MODHW, 9, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
>> + { LLCC_MDMPNG, 21, 512, 0, 1, 0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 },
>> + { LLCC_ECC, 26, 1024, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 },
>> + { LLCC_MODPE, 29, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
>> + { LLCC_APTCM, 30, 512, 3, 1, 0x0, 0xc, 1, 0, 0, 1, 0, 0, 0 },
>> + { LLCC_WRCACHE, 31, 256, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 },
>> +};
>> +
>> +static const struct llcc_slice_config qdu1000_data_8ch[] = {
>> + { LLCC_MDMHPGRW, 7, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
>> + { LLCC_MODHW, 9, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
>> + { LLCC_MDMPNG, 21, 1024, 0, 1, 0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 },
>> + { LLCC_ECC, 26, 2048, 3, 1, 0xffc, 0x0, 0, 0, 0, 0, 1, 0, 0 },
>> + { LLCC_MODPE, 29, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0, 0 },
>> + { LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0xc, 1, 0, 0, 1, 0, 0, 0 },
>> + { LLCC_WRCACHE, 31, 512, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 },
>> +};
>> +
>> static const struct llcc_edac_reg_offset llcc_v1_edac_reg_offset = {
>> .trp_ecc_error_status0 = 0x20344,
>> .trp_ecc_error_status1 = 0x20348,
>> @@ -432,6 +462,37 @@ static const u32 llcc_v2_1_reg_offset[] = {
>> [LLCC_COMMON_STATUS0] = 0x0003400c,
>> };
>>
>> +static const struct qcom_llcc_config qdu1000_cfg[] = {
>> + {
>> + .sct_data = qdu1000_data_8ch,
>> + .size = ARRAY_SIZE(qdu1000_data_8ch),
>> + .need_llcc_cfg = true,
>> + .reg_offset = llcc_v2_1_reg_offset,
>> + .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
>> + },
>> + {
>> + .sct_data = qdu1000_data_4ch,
>> + .size = ARRAY_SIZE(qdu1000_data_4ch),
>> + .need_llcc_cfg = true,
>> + .reg_offset = llcc_v2_1_reg_offset,
>> + .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
>> + },
>> + {
>> + .sct_data = qdu1000_data_4ch,
>> + .size = ARRAY_SIZE(qdu1000_data_4ch),
>> + .need_llcc_cfg = true,
>> + .reg_offset = llcc_v2_1_reg_offset,
>> + .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
>> + },
>> + {
>> + .sct_data = qdu1000_data_2ch,
>> + .size = ARRAY_SIZE(qdu1000_data_2ch),
>> + .need_llcc_cfg = true,
>> + .reg_offset = llcc_v2_1_reg_offset,
>> + .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
>> + },
>> +};
>> +
>> static const struct qcom_llcc_config sc7180_cfg[] = {
>> {
>> .sct_data = sc7180_data,
>> @@ -553,6 +614,11 @@ static const struct qcom_llcc_config
>> sm8550_cfg[] = {
>> },
>> };
>>
>> +static const struct qcom_sct_config qdu1000_cfgs = {
>> + .llcc_config = qdu1000_cfg,
>> + .num_config = 4,
>
> looks like you missed to take konrad suggestion here
>
> https://lore.kernel.org/lkml/2a68b891-b855-1998-3eaf-a21473da0851@linaro.org/
>
Yes, I missed that. Thanks for catching it.
>
> -Mukesh
>
>> +};
>> +
>> static const struct qcom_sct_config sc7180_cfgs = {
>> .llcc_config = sc7180_cfg,
>> .num_config = ARRAY_SIZE(sc7180_cfg),
>> @@ -1171,6 +1237,7 @@ static int qcom_llcc_probe(struct
>> platform_device *pdev)
>> }
>>
>> static const struct of_device_id qcom_llcc_of_match[] = {
>> + { .compatible = "qcom,qdu1000-llcc", .data = &qdu1000_cfgs},
>> { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfgs },
>> { .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfgs },
>> { .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfgs },
>> --
>> 2.41.0
>>
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