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Message-ID: <0aa707b9-8fa0-be00-af8f-dd57828cd336@linaro.org>
Date: Wed, 9 Aug 2023 17:32:39 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Luo Jie <quic_luoj@...cinc.com>, andersson@...nel.org,
agross@...nel.org, konrad.dybcio@...aro.org,
mturquette@...libre.com, sboyd@...nel.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
catalin.marinas@....com, will@...nel.org, p.zabel@...gutronix.de
Cc: linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
quic_srichara@...cinc.com
Subject: Re: [PATCH v1 0/4] add clock controller of qca8386/qca8084
On 09/08/2023 10:00, Luo Jie wrote:
> qca8xxx is 4 * 2.5GBaseT ports chip, working as switch mode
> named by qca8386, or working as PHY mode named by qca8084,
> clock hardware reigster is accessed by MDIO bus.
>
> This patch series add the clock controller of qca8363/qca8084,
> and add the clock ops clk_branch2_qca8k_ops to avoid spin lock
> used during the clock operation of qca8k clock controller where
> the sleep happens when accessing clock control register by MDIO
> bus.
>
> Changes in v1:
> * remove clock flag CLK_ENABLE_MUTEX_LOCK.
> * add clock ops clk_branch2_qca8k_ops.
> * improve yaml file for fixing dtschema warnings.
> * enable clock controller driver in defconfig.
So this is v2, not v1. Your next version, if happens, will be v3, please.
Best regards,
Krzysztof
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