linux-kernel - Re: [PATCH v1 2/4] dt-bindings: clock: add qca8386/qca8084 clock and reset definitions

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <19d885aa-3740-1287-715c-5ecb913c8a72@linaro.org>
Date:   Wed, 9 Aug 2023 17:34:32 +0200
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Luo Jie <quic_luoj@...cinc.com>, andersson@...nel.org,
        agross@...nel.org, konrad.dybcio@...aro.org,
        mturquette@...libre.com, sboyd@...nel.org, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
        catalin.marinas@....com, will@...nel.org, p.zabel@...gutronix.de
Cc:     linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        quic_srichara@...cinc.com
Subject: Re: [PATCH v1 2/4] dt-bindings: clock: add qca8386/qca8084 clock and
 reset definitions

On 09/08/2023 10:00, Luo Jie wrote:
> QCA8386/QCA8084 includes the clock & reset controller that is
> accessed by MDIO bus. Two work modes are supported, qca8386 works
> as switch mode, qca8084 works as PHY mode.
> 
> Signed-off-by: Luo Jie <quic_luoj@...cinc.com>
> ---

Thank you for your patch. There is something to discuss/improve.

> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - const: qcom,qca8084-nsscc
> +      - items:
> +          - enum:
> +              - qcom,qca8085-nsscc
> +              - qcom,qca8082-nsscc
> +              - qcom,qca8386-nsscc
> +              - qcom,qca8385-nsscc
> +              - qcom,qca8384-nsscc

Please keep this enum sorder alphanumerically.

> +          - const: qcom,qca8084-nsscc
> +
> +  clocks:
> +    items:
> +      - description: Chip XO source
> +      - description: UNIPHY0 RX 312P5M/125M clock source
> +      - description: UNIPHY0 TX 312P5M/125M clock source
> +      - description: UNIPHY1 RX 312P5M/125M clock source
> +      - description: UNIPHY1 TX 312P5M/125M clock source
> +      - description: UNIPHY1 RX 312P5M clock source
> +      - description: UNIPHY1 TX 312P5M clock source
> +
> +  reg:
> +    items:
> +      - description: MDIO bus address for Clock & Reset Controller register
> +
> +required:
> +  - compatible
> +  - clocks
> +  - reg
> +
> +allOf:
> +  - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    mdio {
> +      #address-cells = <1>;
> +      #size-cells = <0>;
> +
> +      clock-controller@...000 {
> +        compatible = "qcom,qca8084-nsscc";
> +        reg = <24>;

I think changes from your previous version... Unit address must match
it, so clock-controller@24


> +        clocks = <&qca8k_xo>,
> +                 <&qca8k_uniphy0_rx>,


Best regards,
Krzysztof