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Message-ID: <b695962fa3c3baac08f8be5202e6a5697e7826a0.camel@mediatek.com>
Date: Thu, 10 Aug 2023 12:22:53 +0000
From: Yong Wu (吴勇) <Yong.Wu@...iatek.com>
To: "wenst@...omium.org" <wenst@...omium.org>
CC: "linux-mediatek@...ts.infradead.org"
<linux-mediatek@...ts.infradead.org>,
"robh+dt@...nel.org" <robh+dt@...nel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
Jianjiao Zeng (曾健姣)
<Jianjiao.Zeng@...iatek.com>,
"robin.murphy@....com" <robin.murphy@....com>,
"joro@...tes.org" <joro@...tes.org>,
Chengci Xu (许承赐)
<Chengci.Xu@...iatek.com>,
YF Wang (王云飞) <YF.Wang@...iatek.com>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"iommu@...ts.linux.dev" <iommu@...ts.linux.dev>,
"krzysztof.kozlowski+dt@...aro.org"
<krzysztof.kozlowski+dt@...aro.org>,
"matthias.bgg@...il.com" <matthias.bgg@...il.com>,
Mingyuan Ma (马鸣远)
<Mingyuan.Ma@...iatek.com>,
"angelogioacchino.delregno@...labora.com"
<angelogioacchino.delregno@...labora.com>,
"will@...nel.org" <will@...nel.org>
Subject: Re: [PATCH v12 5/7] iommu/mediatek: Add MT8188 IOMMU Support
On Tue, 2023-08-08 at 17:53 +0800, Chen-Yu Tsai wrote:
>
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> On Fri, Jun 2, 2023 at 5:04 PM Yong Wu <yong.wu@...iatek.com> wrote:
> >
> > From: "Chengci.Xu" <chengci.xu@...iatek.com>
> >
> > MT8188 has 3 IOMMU, containing 2 MM IOMMUs, one is for vdo, the
> other
> > is for vpp. and 1 INFRA IOMMU.
> >
> > Signed-off-by: Chengci.Xu <chengci.xu@...iatek.com>
> > Signed-off-by: Yong Wu <yong.wu@...iatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@...labora.com>
> > ---
> > drivers/iommu/mtk_iommu.c | 49
> +++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 49 insertions(+)
> >
> > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> > index 9c89cf894a4d..5c66af0c45a8 100644
> > --- a/drivers/iommu/mtk_iommu.c
> > +++ b/drivers/iommu/mtk_iommu.c
> > @@ -170,6 +170,7 @@ enum mtk_iommu_plat {
> > M4U_MT8173,
> > M4U_MT8183,
> > M4U_MT8186,
> > + M4U_MT8188,
> > M4U_MT8192,
> > M4U_MT8195,
> > M4U_MT8365,
> > @@ -1593,6 +1594,51 @@ static const struct mtk_iommu_plat_data
> mt8186_data_mm = {
> > .iova_region_larb_msk = mt8186_larb_region_msk,
> > };
> >
> > +static const struct mtk_iommu_plat_data mt8188_data_infra = {
> > + .m4u_plat = M4U_MT8188,
> > + .flags = WR_THROT_EN | DCM_DISABLE |
> STD_AXI_MODE | PM_CLK_AO |
> > + MTK_IOMMU_TYPE_INFRA |
> IFA_IOMMU_PCIE_SUPPORT |
> > + PGTABLE_PA_35_EN |
> CFG_IFA_MASTER_IN_ATF,
>
> FWIW, CFG_IFA_MASTER_IN_ATF should not be tied to the compatible
> string,
> but set via a DT property. The IOMMU controls are secured by
> firmware.
> It is not a property intrinsically tied to the hardware.
The flag CFG_IFA_MASTER_IN_ATF means the registers which enable/disable
iommu are in the secure world. If the master like pcie want to enable
iommu, we have to enter secure world to configure it. It should be HW
intrinsical, right?
>
> If on some other project there is no such security requirement and
> the
> IOMMU is opened up to non-secure world, and ATF not even having
> support
> for the SMC call, this becomes unusable and hard to rectify without
> introducing a new compatible string.
>
> ChenYu
>
> > + .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
> > + .banks_num = 1,
> > + .banks_enable = {true},
> > + .iova_region = single_domain,
> > + .iova_region_nr = ARRAY_SIZE(single_domain),
> > +};
> > +
> > +static const struct mtk_iommu_plat_data mt8188_data_vdo = {
> > + .m4u_plat = M4U_MT8188,
> > + .flags = HAS_BCLK | HAS_SUB_COMM_3BITS |
> OUT_ORDER_WR_EN |
> > + WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE
> |
> > + PGTABLE_PA_35_EN | MTK_IOMMU_TYPE_MM,
> > + .hw_list = &m4ulist,
> > + .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
> > + .banks_num = 1,
> > + .banks_enable = {true},
> > + .iova_region = mt8192_multi_dom,
> > + .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
> > + .larbid_remap = {{2}, {0}, {21}, {0}, {19}, {9, 10,
> > + 11 /* 11a */, 25 /* 11c */},
> > + {13, 0, 29 /* 16b */, 30 /* 17b */, 0},
> {5}},
> > +};
> > +
> > +static const struct mtk_iommu_plat_data mt8188_data_vpp = {
> > + .m4u_plat = M4U_MT8188,
> > + .flags = HAS_BCLK | HAS_SUB_COMM_3BITS |
> OUT_ORDER_WR_EN |
> > + WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE
> |
> > + PGTABLE_PA_35_EN | MTK_IOMMU_TYPE_MM,
> > + .hw_list = &m4ulist,
> > + .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
> > + .banks_num = 1,
> > + .banks_enable = {true},
> > + .iova_region = mt8192_multi_dom,
> > + .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
> > + .larbid_remap = {{1}, {3}, {23}, {7},
> {MTK_INVALID_LARBID},
> > + {12, 15, 24 /* 11b */}, {14,
> MTK_INVALID_LARBID,
> > + 16 /* 16a */, 17 /* 17a */,
> MTK_INVALID_LARBID,
> > + 27, 28 /* ccu0 */, MTK_INVALID_LARBID},
> {4, 6}},
> > +};
> > +
> > static const unsigned int
> mt8192_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] =
> {
> > [0] = {~0, ~0}, /* Region0: larb0/1
> */
> > [1] = {0, 0, 0, 0, ~0, ~0, 0, ~0}, /* Region1:
> larb4/5/7 */
> > @@ -1701,6 +1747,9 @@ static const struct of_device_id
> mtk_iommu_of_ids[] = {
> > { .compatible = "mediatek,mt8173-m4u", .data =
> &mt8173_data},
> > { .compatible = "mediatek,mt8183-m4u", .data =
> &mt8183_data},
> > { .compatible = "mediatek,mt8186-iommu-mm", .data =
> &mt8186_data_mm}, /* mm: m4u */
> > + { .compatible = "mediatek,mt8188-iommu-infra", .data =
> &mt8188_data_infra},
> > + { .compatible = "mediatek,mt8188-iommu-vdo", .data =
> &mt8188_data_vdo},
> > + { .compatible = "mediatek,mt8188-iommu-vpp", .data =
> &mt8188_data_vpp},
> > { .compatible = "mediatek,mt8192-m4u", .data =
> &mt8192_data},
> > { .compatible = "mediatek,mt8195-iommu-infra", .data =
> &mt8195_data_infra},
> > { .compatible = "mediatek,mt8195-iommu-vdo", .data =
> &mt8195_data_vdo},
> > --
> > 2.25.1
> >
> >
>
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