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Message-ID: <20230811-jiffy-nebula-a8ea5ef15eee@wendy>
Date: Fri, 11 Aug 2023 07:43:43 +0100
From: Conor Dooley <conor.dooley@...rochip.com>
To: Xingyu Wu <xingyu.wu@...rfivetech.com>
CC: Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Emil Renner Berthing <emil.renner.berthing@...onical.com>,
Conor Dooley <conor@...nel.org>,
Hal Feng <hal.feng@...rfivetech.com>,
<linux-kernel@...r.kernel.org>, <linux-clk@...r.kernel.org>
Subject: Re: [PATCH v1] clk: starfive: jh7110-sys: Set PLL0 rate to 1.5GHz
On Fri, Aug 11, 2023 at 11:36:31AM +0800, Xingyu Wu wrote:
> Set PLL0 rate to 1.5GHz.
Why are you doing that though?
> Change the parent of cpu_root clock
> and the divider of cpu_core before setting.
>
> Signed-off-by: Xingyu Wu <xingyu.wu@...rfivetech.com>
> ---
>
> Hi Stephen and Emil,
>
> This patch sets PLL0 rate to 1.5GHz. In order not to affect the cpu
> operation, the cpu_root's parent clock should be changed first.
> And the divider of the cpu_core clock should be set to 2 so they
> won't crash when setting 1.5GHz without voltage regulation.
>
> This patch is based on linux-next which has merge PLL driver on
> StarFive JH7110 SoC.
>
> Thanks,
> Xingyu Wu
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