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Message-ID: <CAMRc=Mc00yy6DxdEos_w7HAkAwH7j0HBvkbQbaQiA_wTXiwFUg@mail.gmail.com>
Date: Fri, 11 Aug 2023 16:25:47 +0200
From: Bartosz Golaszewski <brgl@...ev.pl>
To: Yinbo Zhu <zhuyinbo@...ngson.cn>
Cc: Conor Dooley <conor@...nel.org>,
Linus Walleij <linus.walleij@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>, linux-gpio@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Jianmin Lv <lvjianmin@...ngson.cn>, wanghongliang@...ngson.cn,
loongson-kernel@...ts.loongnix.cn
Subject: Re: [PATCH v3 1/2] gpio: dt-bindings: add parsing of loongson gpio offset
On Thu, Aug 10, 2023 at 8:19 AM Yinbo Zhu <zhuyinbo@...ngson.cn> wrote:
>
>
>
> 在 2023/8/9 下午11:39, Conor Dooley 写道:
> > On Wed, Aug 09, 2023 at 03:47:55PM +0800, Yinbo Zhu wrote:
> >> 在 2023/8/8 下午8:05, Conor Dooley 写道:
> >>> On Mon, Aug 07, 2023 at 03:40:42PM +0800, Yinbo Zhu wrote:
> >
> >>>> + loongson,gpio-ctrl-mode:
> >>>> + $ref: /schemas/types.yaml#/definitions/uint32
> >>>> + description:
> >>>> + This option indicate this GPIO control mode, where '0' represents
> >>>> + bit control mode and '1' represents byte control mode.
> >>>
> >>> How is one supposed to know which of these modes to use?
> >>
> >>
> >> Byte mode is to access by byte, such as gpio3, the base address of the
> >> gpio controller is offset by 3 bytes as the access address of gpio3.
> >>
> >> The bit mode is the normal mode that like other platform gpio and it is
> >> to access by bit.
> >>
> >> If both modes are supported, it is recommended to prioritize using byte
> >> mode that according to spec.
> >
> > So, sounds like this property should instead be a boolean that notes
> > whether the hardware supports the mode or not, rather than the current
> > enum used to determine software policy.
>
>
> okay, I got it, I will use boolean,
>
Why do you want to put it into device-tree so badly? This is not the
first driver that would have of_match_data for different variants
where you can have a structure that would keep offsets for different
models. It's not like you will have hundreds of "compatible" chips
anyway, most likely just a few?
Bart
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