linux-kernel - [PATCH v6 0/4] perf: arm_cspmu: ampere: Add support for Ampere SoC PMUs

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Message-ID: <20230815063526.9022-1-ilkka@os.amperecomputing.com>
Date:   Mon, 14 Aug 2023 23:35:22 -0700
From:   Ilkka Koskinen <ilkka@...amperecomputing.com>
To:     Will Deacon <will@...nel.org>, Robin Murphy <robin.murphy@....com>,
        Besar Wicaksono <bwicaksono@...dia.com>,
        Jonathan Cameron <Jonathan.Cameron@...wei.com>,
        Suzuki K Poulose <suzuki.poulose@....com>,
        Mark Rutland <mark.rutland@....com>,
        Jonathan Corbet <corbet@....net>
Cc:     Ilkka Koskinen <ilkka@...amperecomputing.com>,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-doc@...r.kernel.org
Subject: [PATCH v6 0/4] perf: arm_cspmu: ampere: Add support for Ampere SoC PMUs

Changes since v5:
    * Implemented the needed parts for vendor registration API
    * Rebased on top of Besar's patch 

      [PATCH v5] perf: arm_cspmu: Separate Arm and vendor module
      https://lore.kernel.org/all/20230705104745.52255-1-bwicaksono@nvidia.com/

    * v5: https://lore.kernel.org/all/20230714010141.824226-1-ilkka@os.amperecomputing.com/

Changes since v4:
    * "Support implementation specific filters" patch:
        - Added comment about filter and impdef registers and reference
          to the Coresight PMU specification to the commit message

    * "Add support for Ampere SoC PMU" patch:
	- Fixed the documentation and added more comments
        - Changed the incrementing PMU index number to idr_alloc()
	  (Needs a impdef release hook patch to release unused index)
	- Fixed style in init_ops() to more reasonable
	- Moved bank parameter to config1

Changes since v3:
    * use_64b_counter_reg => has_atomic_dword (patch 1/4)
    * Removed the unnecessary hook for group validation (patch 3/4)
    * Added group config validation to ampere_cspmu_validate_event() (patch 4/4)
    * Rebased the patchset

Changes since v2:
    * Changed to use supports_64bits_atomics() and replaced the split writes
      with lo_hi_writeq()
    * Added implementation specific group validation to patch 3
    * Dropped shared interrupt patch
    * Removed unnecessary filter_enable parameter from ampere module
    * Added group validation to ampere module

Changes since v1:
    * Rather than creating a completely new driver, implemented as a submodule
      of Arm CoreSight PMU driver
      * Fixed shared filter handling

Ilkka Koskinen (4):
  perf: arm_cspmu: Split 64-bit write to 32-bit writes
  perf: arm_cspmu: Support implementation specific filters
  perf: arm_cspmu: Support implementation specific validation
  perf: arm_cspmu: ampere_cspmu: Add support for Ampere SoC PMU

 .../admin-guide/perf/ampere_cspmu.rst         |  29 ++
 drivers/perf/arm_cspmu/Kconfig                |  10 +
 drivers/perf/arm_cspmu/Makefile               |   2 +
 drivers/perf/arm_cspmu/ampere_cspmu.c         | 271 ++++++++++++++++++
 drivers/perf/arm_cspmu/arm_cspmu.c            |  33 ++-
 drivers/perf/arm_cspmu/arm_cspmu.h            |   7 +
 6 files changed, 346 insertions(+), 6 deletions(-)
 create mode 100644 Documentation/admin-guide/perf/ampere_cspmu.rst
 create mode 100644 drivers/perf/arm_cspmu/ampere_cspmu.c

-- 
2.41.0