linux-kernel - [tip: x86/urgent] x86/srso: Explain the untraining sequences a bit more

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Message-ID: <169217251418.27769.2623579948793879056.tip-bot2@tip-bot2>
Date:   Wed, 16 Aug 2023 07:55:14 -0000
From:   "tip-bot2 for Borislav Petkov (AMD)" <tip-bot2@...utronix.de>
To:     linux-tip-commits@...r.kernel.org
Cc:     "Borislav Petkov (AMD)" <bp@...en8.de>, x86@...nel.org,
        linux-kernel@...r.kernel.org
Subject: [tip: x86/urgent] x86/srso: Explain the untraining sequences a bit more

The following commit has been merged into the x86/urgent branch of tip:

Commit-ID:     d80c3c9de067e08498d9bbfef7ab0b716fe4cc05
Gitweb:        https://git.kernel.org/tip/d80c3c9de067e08498d9bbfef7ab0b716fe4cc05
Author:        Borislav Petkov (AMD) <bp@...en8.de>
AuthorDate:    Mon, 14 Aug 2023 21:29:50 +02:00
Committer:     Borislav Petkov (AMD) <bp@...en8.de>
CommitterDate: Wed, 16 Aug 2023 09:39:17 +02:00

x86/srso: Explain the untraining sequences a bit more

The goal is to eventually have a proper documentation about all this.

Signed-off-by: Borislav Petkov (AMD) <bp@...en8.de>
Link: https://lore.kernel.org/r/20230814164447.GFZNpZ/64H4lENIe94@fat_crate.local
---
 arch/x86/lib/retpoline.S | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/x86/lib/retpoline.S b/arch/x86/lib/retpoline.S
index 5e85da1..cd86aeb 100644
--- a/arch/x86/lib/retpoline.S
+++ b/arch/x86/lib/retpoline.S
@@ -187,6 +187,25 @@ SYM_CODE_START(srso_alias_return_thunk)
 SYM_CODE_END(srso_alias_return_thunk)
 
 /*
+ * Some generic notes on the untraining sequences:
+ *
+ * They are interchangeable when it comes to flushing potentially wrong
+ * RET predictions from the BTB.
+ *
+ * The SRSO Zen1/2 (MOVABS) untraining sequence is longer than the
+ * Retbleed sequence because the return sequence done there
+ * (srso_safe_ret()) is longer and the return sequence must fully nest
+ * (end before) the untraining sequence. Therefore, the untraining
+ * sequence must fully overlap the return sequence.
+ *
+ * Regarding alignment - the instructions which need to be untrained,
+ * must all start at a cacheline boundary for Zen1/2 generations. That
+ * is, instruction sequences starting at srso_safe_ret() and
+ * the respective instruction sequences at retbleed_return_thunk()
+ * must start at a cacheline boundary.
+ */
+
+/*
  * Safety details here pertain to the AMD Zen{1,2} microarchitecture:
  * 1) The RET at retbleed_return_thunk must be on a 64 byte boundary, for
  *    alignment within the BTB.