lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <928822fd-642a-5ca7-7b42-dc7885f3cf51@arm.com>
Date:   Thu, 17 Aug 2023 17:35:34 +0100
From:   Robin Murphy <robin.murphy@....com>
To:     Michael Shavit <mshavit@...gle.com>, iommu@...ts.linux.dev
Cc:     Jason Gunthorpe <jgg@...pe.ca>,
        Jean-Philippe Brucker <jean-philippe@...aro.org>,
        Joerg Roedel <joro@...tes.org>,
        Lu Baolu <baolu.lu@...ux.intel.com>,
        Nicolin Chen <nicolinc@...dia.com>,
        Tomas Krcka <krckatom@...zon.de>,
        Will Deacon <will@...nel.org>,
        Yicong Yang <yangyicong@...ilicon.com>,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] iommu/arm-smmu-v3: Simplify stage selection logic

On 2023-08-17 17:03, Michael Shavit wrote:
> It is invalid for an arm-smmu-v3 to have neither FEAT_TRANS_S1 nor
> FEAT_TRANS_S2 bits set, and this is even checked in the probe.
> 
> Only set ARM_SMMU_DOMAIN_S2 if FEAT_TRANS_S1 isn't supported, otherwise set
> ARM_SMMU_DOMAIN_S1. This is clearer as the existing code implies that
> something more sophisticated is going on with the stage selection logic.

The reason it's like this is because of arm_smmu_enable_nesting(), which 
*is* the additional thing that's going on with the stage selection logic.

Thanks,
Robin.

> Signed-off-by: Michael Shavit <mshavit@...gle.com>
> ---
> 
>   drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> index 9b0dc35056019..e74c8c630adfa 100644
> --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> @@ -2206,7 +2206,7 @@ static int arm_smmu_domain_finalise(struct iommu_domain *domain,
>   	/* Restrict the stage to what we can actually support */
>   	if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1))
>   		smmu_domain->stage = ARM_SMMU_DOMAIN_S2;
> -	if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2))
> +	else
>   		smmu_domain->stage = ARM_SMMU_DOMAIN_S1;
>   
>   	switch (smmu_domain->stage) {
> 
> base-commit: 6eaae198076080886b9e7d57f4ae06fa782f90ef

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ