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Message-ID: <ZN5I88rsUHb693H/@Asurada-Nvidia>
Date:   Thu, 17 Aug 2023 09:21:07 -0700
From:   Nicolin Chen <nicolinc@...dia.com>
To:     Michael Shavit <mshavit@...gle.com>
CC:     <iommu@...ts.linux.dev>, Jason Gunthorpe <jgg@...pe.ca>,
        "Jean-Philippe Brucker" <jean-philippe@...aro.org>,
        Joerg Roedel <joro@...tes.org>,
        Lu Baolu <baolu.lu@...ux.intel.com>,
        Robin Murphy <robin.murphy@....com>,
        Tomas Krcka <krckatom@...zon.de>,
        Will Deacon <will@...nel.org>,
        Yicong Yang <yangyicong@...ilicon.com>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] iommu/arm-smmu-v3: Simplify stage selection logic

On Fri, Aug 18, 2023 at 12:03:30AM +0800, Michael Shavit wrote:

> It is invalid for an arm-smmu-v3 to have neither FEAT_TRANS_S1 nor
> FEAT_TRANS_S2 bits set, and this is even checked in the probe.
> 
> Only set ARM_SMMU_DOMAIN_S2 if FEAT_TRANS_S1 isn't supported, otherwise set
> ARM_SMMU_DOMAIN_S1. This is clearer as the existing code implies that
> something more sophisticated is going on with the stage selection logic.
> 
> Signed-off-by: Michael Shavit <mshavit@...gle.com>

Reviewed-by: Nicolin Chen <nicolinc@...dia.com>

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