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Date:   Mon, 21 Aug 2023 20:46:17 +0200
From:   "Rafael J. Wysocki" <rafael@...nel.org>
To:     Mario Limonciello <mario.limonciello@....com>
Cc:     Mika Westerberg <mika.westerberg@...ux.intel.com>,
        "Rafael J . Wysocki" <rafael@...nel.org>,
        Bjorn Helgaas <helgaas@...nel.org>, linux-pci@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-acpi@...r.kernel.org,
        Iain Lane <iain@...ngesquash.org.uk>,
        Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
        Kuppuswamy Sathyanarayanan 
        <sathyanarayanan.kuppuswamy@...ux.intel.com>
Subject: Re: [PATCH v14.c 4/4] PCI: ACPI: Limit the Intel specific opt-in to
 D3 to 2024

On Fri, Aug 18, 2023 at 9:40 PM Mario Limonciello
<mario.limonciello@....com> wrote:
>
> Intel systems that need to have PCIe ports in D3 for low power idle
> specify this by constraints on the ACPI PNP0D80 device. As this information
> is queried by acpi_pci_bridge_d3(), limit the DMI BIOS year check to stop
> at 2024. This will allow future systems to rely on the constraints check
> and ACPI checks to set up policy like non-Intel systems do.

So I'm not sure about the value of this change.

The behavior is made Intel-specific in [14a 1/1] and it will be that
way at least for some time.  This change only sets the date after
which it won't be Intel-specific any more, but for what reason
exactly?

And why is 2024 the cut-off year (and not 2025, for example)?

If Intel platforms continue to be OK with putting all PCIe ports into
D3hot beyond 2024, why restrict the kernel from doing so on them?

> Signed-off-by: Mario Limonciello <mario.limonciello@....com>
> ---
> v13->v14:
>  * Use a variable instead
> v12->v13:
>  * New patch
> ---
>  drivers/pci/pci.c | 14 ++++++++++----
>  1 file changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index bfdad2eb36d13..c8787d898c377 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -3037,16 +3037,22 @@ bool pci_bridge_d3_possible(struct pci_dev *bridge)
>                         return false;
>
>                 /*
> -                * Allow Intel PCIe ports from 2015 onward to go into D3 to
> +                * Allow Intel PCIe ports from 2015 to 2024 to go into D3 to
>                  * achieve additional energy conservation on some platforms.
>                  *
> +                * Intel systems from 2025 onward that need this are expected
> +                * to specify this in an LPS0 device constraint instead.
> +                *
>                  * This is only set for Intel PCIe ports as it causes problems
>                  * on both AMD Rembrandt and Phoenix platforms where USB keyboards
>                  * can not be used to wake the system from suspend.
>                  */
> -               if (bridge->vendor == PCI_VENDOR_ID_INTEL &&
> -                   dmi_get_bios_year() >= 2015)
> -                       return true;
> +               if (bridge->vendor == PCI_VENDOR_ID_INTEL) {
> +                       int year = dmi_get_bios_year();
> +
> +                       if (year >= 2015 && year <= 2024)
> +                               return true;
> +               }
>                 break;
>         }
>
> --
> 2.34.1
>

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